Quantum computers (QC) promise to solve certain computational problems exponentially faster than a classical computer due to the superposition and entanglement properties of quantum bits (qubits). Among several qubit technologies, spin qubits are a promising candidate for large-scale QC, since (1) they have a small footprint allowing them to be densely integrated and (2) they can operate at relatively high temperatures (>1K) [1], potentially reducing system cost and complexity.
Quantum computers (QC) promise to solve certain computational problems exponentially faster than a classical computer due to the superposition and entanglement properties of quantum bits (qubits). Among several qubit technologies, spin qubits are a promising candidate for large-scale QC, since (1) they have a small footprint allowing them to be densely integrated and (2) they can operate at relatively high temperatures (>1K) [1], potentially reducing system cost and complexity.
Quantum computing holds the promise to solve many of today's intractable problems. A solid-state quantum computer (QC) is generally made of an array of qubits implemented in one of many solid-state technologies and operating at deep-cryogenic temperatures (10-to-20mK). Silicon spin qubits are a promising candidate for scalable QCs, due to their size, long coherence times and potential for co-integration with the required classical control and readout electronics. Recently, semiconductor spin qubits have been demonstrated to operate at ~1K, thus accelerating the achievement of a compact QC [1]. Classical qubit control electronics has also progressed, with the demonstration of fully-integrated control of spin qubits [2] and transmons [3] implemented in a cryo-CMOS technology. While a cryo-CMOS integrated circuit has been co-integrated with quantum dots [4], fully-integrated readout electronics has not yet been addressed in the literature.
Quantum computers (QCs) promise significant speedup for relevant computational problems that are intractable by classical computers. QCs process information stored in quantum bits (qubits) that must be typically cooled down to cryogenic temperatures. Since state-of-the-art QCs employ only a few qubits, those qubits can be driven and read out by room-temperature electronics connected to the cryogenic qubits by only a few wires. However, practical QCs will require more than thousands of qubits, making this approach impractical due to system complexity and reliability concerns. Although frequency multiplexing would reduce the interconnects to room temperature by fitting many qubit channels in the same physical interconnect, an excessive number of interconnects would still be required. An alternative, more scalable solution is a cryogenic electronic interface operating very close to the quantum processor to keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnect to room temperature. This system must comprise drivers, readout circuits (LNAs, ADCs), and a digital controller to steer the quantum-algorithm execution [1]. While cryogenic CMOS (cryo-CMOS) wideband drivers and LNAs supporting qubit frequency multiplexing have been shown before [1] -[3], no wideband cryo-CMOS ADC has been demonstrated yet.
Cryogenic CMOS (cryo-CMOS) support of quantum processors is becoming a necessity to ensure the continuous growth of qubit count, so as to achieve scalable, fault-tolerant quantum computers. The first paper of the session describes an integrated controller for spin qubits that performs state manipulation, readout, and gate pulsing fabricated in 22nm FinFET CMOS technology. The second paper presents a fully integrated SoC for spin qubit interface based on RF reflectometry of quantum dots, all implemented in 40nm CMOS technology, for scalable quantum systems operating at 3.5K. The third paper also focuses on scalable RF based readout of spin qubits for a record 0.17mW/qubit power requirement, operating at 4.2K. The fourth paper proposes a 1GS/s A/D converter for low-power digitization of the signal measured from a qubit readout that achieves a FOM of 15fJ/conv.-step at 4K.
Spin qubits are a promising candidate for large-scale fault-tolerant quantum computing due to2footprint per qubit, higher operating temperature (up to 1K [1]) and possible compatibility with industrial CMOS processes [2], [3]. However, the need for a simultaneous ~µs readout of thousands of devices is especially challenging in terms of power consumption and footprint per qubit [4], [5]. Frequency-domain multiplexed (FDM) reflectometry architectures using cryo-CMOS have been introduced in [6], [7], [8] but these circuits require bulky > 100µm2inductors and do not match readout time specifications using actual quantum devices. Besides, current integrator readout schemes have been proposed [9], [10], but offer no scaling perspectives beyond time-domain multiplexing, leading to strong constraints in terms of bandwidth and power consumption. Recently, [4] introduced a capacitive-feedback transimpedance amplifier achieving an inductor-less FDM readout of two quantum dots [11]. Nevertheless, the demonstrated power consumption per qubit of 214µW/qubit remains too high to match the maximum heat dissipation allowed near quantum devices [12] in a large-scale perspective. Moreover, the used On-Off Keying (OOK) modulations are limited to one qubit per carrier, thus requiring high bandwidth and power consumption in order to read thousands of qubits.
Quantum computers (QCs) can perform certain computational problems exponentially faster than classical computers due to the superposition and entanglement properties of quantum bits (qubits). Among the various qubit technologies, superconducting qubits offer the fastest computational speed and are easy to fabricate, making them a strong candidate for large-scale QC systems with the potential to reduce both cost and complexity [1]. To execute practical quantum algorithms with real-time quantum error correction, thousands of qubits must be simultaneously controlled and read out much faster than the coherence time of the qubits (≪∼120μs). Current approaches require thousands of cables connecting the qubits to bulky room temperature (RT) equipment, which severely limits the scalability of control and readout electronics for QC systems with more than 103 qubits. To address this issue, the electronic interfaces must be placed in close proximity to the qubits, or ideally co-integrated and operated at similar cryogenic temperatures (CTs) with the qubits [1, 2]. This work proposes a 4 -to7 GHz single-chip fully integrated readout integrated circuit (ROIC) with 48 K noise temperature measured at 26K,253MHzIF bandwidth (BW), and 52.3 dB spurious-free dynamic range (SFDR) for compatibility with superconducting multi-qubits read-out.
Large-scale quantum computing holds promise for exponentially faster computation speed to address currently unsolvable problems. Nevertheless, biasing, driving and reading numerous physical qubits operating at cryogenic temperature remains an on-going challenge. In particular, the integration of cryogenic control and readout ICs appears mandatory to overcome the wiring bottleneck [1]–[3]. In this regard, the promising higher operating temperature (up to 1K) of silicon semiconductor qubits offers a more substantial cryogenic power budget, which could enable addressing larger qubit arrays with integrated cryogenic CMOS electronics. In the context of 100,000 qubits at 1K, the maximum power consumption allowed by cooling capability is about 1W within a compact footprint of just a few cm2, defining targets of2/qubit footprint. Focusing on the readout IC, the semiconductor-qubit coherence time also imposes a typical3.