Quantum computers hold a promise to solve intractable problems that can not be solved with classical computers. In quantum computers, information is processed in qubits as opposed to bits. The proper operation of qubits requires them to be operated in a quantum state; hence they need to be cooled down to temperatures well below l1K. Using qubits and their quantum mechanical property, quantum computers can achieve exponential speedup in solving certain computing problems compared to classical computers. However, this can only be achieved by employing thousands of qubits. At the current state of play, quantum computers are still far from practical. The current state-of-the-art solution dictates that each qubit needs multiple interconnects towards room temperature and requires bulky room temperature instruments for qubit readout and control. Clearly, this current solution will not scale well for a quantum computer with many qubits. In an effort to solve this issue, it has been proposed to realize dedicated integrated circuits for control and readout of the qubits and operate them closer to the qubits' operating temperature to enable scalability. The thesis presents the implementation of an integrated RF receiver for spin and superconducting qubit readout applications. The work aims to replace the bulky room temperature electronics with an integrated solution that operates at 4K to enable scalability and simplification of the quantum computing architecture. The receiver has been designed in the TSMC 40nm CMOS technology and has been characterized in room temperature and 4K. The measured performance shows that the receiver features a gain of 58 dB and a minimum double-sideband noise figure of 0.6 dB at 4K with an operating frequency of 6-8 GHz; a comparable performance to the current state-of-the-art room temperature electronics used for qubit readout. Moreover, this work demonstrates a qubit readout experiment with the integrated receiver in both room temperature and 4K. The qubit readout experiment shows a comparable qubit readout performance with the integrated receiver at room temperature. However, due to oscillation problems, a degradation in qubit readout performance with the chip operating at 4K is observed.
Quantum computers hold a promise to solve intractable problems that can not be solved with classical computers. In quantum computers, information is processed in qubits as opposed to bits. The proper operation of qubits requires them to be operated in a quantum state; hence they need to be cooled down to temperatures well below l1K. Using qubits and their quantum mechanical property, quantum computers can achieve exponential speedup in solving certain computing problems compared to classical computers. However, this can only be achieved by employing thousands of qubits. At the current state of play, quantum computers are still far from practical. The current state-of-the-art solution dictates that each qubit needs multiple interconnects towards room temperature and requires bulky room temperature instruments for qubit readout and control. Clearly, this current solution will not scale well for a quantum computer with many qubits. In an effort to solve this issue, it has been proposed to realize dedicated integrated circuits for control and readout of the qubits and operate them closer to the qubits' operating temperature to enable scalability. The thesis presents the implementation of an integrated RF receiver for spin and superconducting qubit readout applications. The work aims to replace the bulky room temperature electronics with an integrated solution that operates at 4K to enable scalability and simplification of the quantum computing architecture. The receiver has been designed in the TSMC 40nm CMOS technology and has been characterized in room temperature and 4K. The measured performance shows that the receiver features a gain of 58 dB and a minimum double-sideband noise figure of 0.6 dB at 4K with an operating frequency of 6-8 GHz; a comparable performance to the current state-of-the-art room temperature electronics used for qubit readout. Moreover, this work demonstrates a qubit readout experiment with the integrated receiver in both room temperature and 4K. The qubit readout experiment shows a comparable qubit readout performance with the integrated receiver at room temperature. However, due to oscillation problems, a degradation in qubit readout performance with the chip operating at 4K is observed.
Quantum computing holds the promise to solve problems that are currently intractable by classical computing platforms. Such computing framework relies on the properties of quantum bits (qubits) that operates at cryogenic temperatures well below 1K. Besides a quantum processor, an operational quantum computer needs a classical electronic controller reading out the electrical signals generated by the qubits and the providing electrical control to perform the required operations on the qubits. Since today’s quantum processors comprise a low number of qubits (<10), most controlling electronics can operate at room temperature and be connected by bulky interconnects to the cryogenic qubit chamber. However, when scaling up to the thousands of qubits required in a practical quantum algorithm, the classical electronics must be placed at cryogenic temperature to simplify the interconnects and allow a compact, reliable and scalable system. In this work, we propose the fully-integrated implementation in standard CMOS technology of the electronic read-out for spin qubits. Simulations show that the proposed current read-out circuit can achieve a 10MHz bandwidth that is 10X wider than current state-of-the-art read-outs while keeping comparable noise performance and operating at 4.2K. Such results are a promising indication that cryogenic CMOS circuits can provide the building blocks for the integration of the classical electronic controller for future scalable quantum computers.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Engineering research in quantum computing is geared towards building a ”useful” quantum computer; usefulness here refers to the capability of solving computation problems that hold significant value in commercial applications, but are currently impossible to do in reasonable time-frames using classical algorithms. This is fundamentally a problem of scale – problems that can be solved by few-qubit processors can also be readily simulated by classical supercomputers in realistic time-frames, but as these problems grow in complexity, quantum computers are believed to be able to provide an exponential speedup over their classical counterparts, the so-called quantum advantage. However, scaling quantum computers presents many challenges due to the need to perform complex signal control and data processing at nanosecond time scales on fragile quantum systems that need stringent degrees of isolation from the environment for the computations to be carried out with high fidelity. Some of the most promising implementations of experimental-grade quantum computers are maintained in cryogenic environments due to the fact that at low enough temperatures noise processes due to random thermal excitations can be minimized. However, the control and measurement of quantum processors is currently done by systems at room temperature, whose connections to the cryogenic environment present thermal loading that will need to be addressed as these processors scale and their IO requirements to co-processors grow in complexity. As such, one possible path to scaling co-processing capabilities without compromising the quantum processor’s performance is the partial or complete integration of the co-processor in the cryo-environment. Several works describe systems that aim to do just that; and ”Cryo-CMOS” has become an important research subspace. This thesis aims to add to the current advancements in this field, specifically in the area of qubit measurements. It culminates in the implementation of a radio receiver that leverages the advantages of BiCMOS technology in cryo-environments to measure the state of a superconducting transmon-based qubit while strapped to a 4K stage in a dilution refrigerator. Critically, we demonstrate that low-noise amplification, down-conversion, and demodulation can all be done in the cryo-environment on a constrained power budget, with high fidelity comparable to a state-of-the-art (InP-HEMT LNA-based) qubit readout system, when preceded by a high-gain, quantum-noise-limited Josephson parametric amplifier.
Quantum computers (QCs) can perform certain computational problems exponentially faster than classical computers due to the superposition and entanglement properties of quantum bits (qubits). Among the various qubit technologies, superconducting qubits offer the fastest computational speed and are easy to fabricate, making them a strong candidate for large-scale QC systems with the potential to reduce both cost and complexity [1]. To execute practical quantum algorithms with real-time quantum error correction, thousands of qubits must be simultaneously controlled and read out much faster than the coherence time of the qubits (≪∼120μs). Current approaches require thousands of cables connecting the qubits to bulky room temperature (RT) equipment, which severely limits the scalability of control and readout electronics for QC systems with more than 103 qubits. To address this issue, the electronic interfaces must be placed in close proximity to the qubits, or ideally co-integrated and operated at similar cryogenic temperatures (CTs) with the qubits [1, 2]. This work proposes a 4 -to7 GHz single-chip fully integrated readout integrated circuit (ROIC) with 48 K noise temperature measured at 26K,253MHzIF bandwidth (BW), and 52.3 dB spurious-free dynamic range (SFDR) for compatibility with superconducting multi-qubits read-out.
In the pursuit of quantum computing, solid-state quantum systems, particularly superconducting ones, have made remarkable advancements over the past two decades. However, achieving fault-tolerant quantum computing for next-generation applications necessitates the integration of several million qubits, which presents significant challenges in terms of interconnection complexity and latency that are currently unsolvable with state-of-the-art room-temperature control and readout electronics. Recently, cryogenic integrated circuits (ICs), including CMOS radio-frequency ICs and rapid-single-flux-quantum-logic ICs, have emerged as potential alternatives to room-temperature electronics. Unlike their room-temperature counterparts, these ICs are deployed within cryostats to enhance scalability by reducing the number and length of transmission lines. Additionally, operating at cryogenic temperatures can suppress electronic noise and improve qubit control fidelity. However, for CMOS ICs specifically, circuit design uncertainties arise due to a lack of reliable models for cryogenic field effect transistors as well as issues related to severe fickle noises and power dissipation at cryogenic temperatures. This paper provides a comprehensive review of recent research on both types of cryogenic control and readout ICs but primarily focuses on the more mature CMOS technology. The discussion encompasses principles underlying control and readout techniques employed in cryogenic CMOS ICs along with their architectural designs; characterization and modeling approaches for field effect transistors under cryogenic conditions; as well as fundamental concepts pertaining to rapid single flux quantum circuits.
A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3digitally controlled oscillator required to manipulate the state of qubits.