Engineering research in quantum computing is geared towards building a ”useful” quantum computer; usefulness here refers to the capability of solving computation problems that hold significant value in commercial applications, but are currently impossible to do in reasonable time-frames using classical algorithms. This is fundamentally a problem of scale – problems that can be solved by few-qubit processors can also be readily simulated by classical supercomputers in realistic time-frames, but as these problems grow in complexity, quantum computers are believed to be able to provide an exponential speedup over their classical counterparts, the so-called quantum advantage. However, scaling quantum computers presents many challenges due to the need to perform complex signal control and data processing at nanosecond time scales on fragile quantum systems that need stringent degrees of isolation from the environment for the computations to be carried out with high fidelity. Some of the most promising implementations of experimental-grade quantum computers are maintained in cryogenic environments due to the fact that at low enough temperatures noise processes due to random thermal excitations can be minimized. However, the control and measurement of quantum processors is currently done by systems at room temperature, whose connections to the cryogenic environment present thermal loading that will need to be addressed as these processors scale and their IO requirements to co-processors grow in complexity. As such, one possible path to scaling co-processing capabilities without compromising the quantum processor’s performance is the partial or complete integration of the co-processor in the cryo-environment. Several works describe systems that aim to do just that; and ”Cryo-CMOS” has become an important research subspace. This thesis aims to add to the current advancements in this field, specifically in the area of qubit measurements. It culminates in the implementation of a radio receiver that leverages the advantages of BiCMOS technology in cryo-environments to measure the state of a superconducting transmon-based qubit while strapped to a 4K stage in a dilution refrigerator. Critically, we demonstrate that low-noise amplification, down-conversion, and demodulation can all be done in the cryo-environment on a constrained power budget, with high fidelity comparable to a state-of-the-art (InP-HEMT LNA-based) qubit readout system, when preceded by a high-gain, quantum-noise-limited Josephson parametric amplifier.
Engineering research in quantum computing is geared towards building a ”useful” quantum computer; usefulness here refers to the capability of solving computation problems that hold significant value in commercial applications, but are currently impossible to do in reasonable time-frames using classical algorithms. This is fundamentally a problem of scale – problems that can be solved by few-qubit processors can also be readily simulated by classical supercomputers in realistic time-frames, but as these problems grow in complexity, quantum computers are believed to be able to provide an exponential speedup over their classical counterparts, the so-called quantum advantage. However, scaling quantum computers presents many challenges due to the need to perform complex signal control and data processing at nanosecond time scales on fragile quantum systems that need stringent degrees of isolation from the environment for the computations to be carried out with high fidelity. Some of the most promising implementations of experimental-grade quantum computers are maintained in cryogenic environments due to the fact that at low enough temperatures noise processes due to random thermal excitations can be minimized. However, the control and measurement of quantum processors is currently done by systems at room temperature, whose connections to the cryogenic environment present thermal loading that will need to be addressed as these processors scale and their IO requirements to co-processors grow in complexity. As such, one possible path to scaling co-processing capabilities without compromising the quantum processor’s performance is the partial or complete integration of the co-processor in the cryo-environment. Several works describe systems that aim to do just that; and ”Cryo-CMOS” has become an important research subspace. This thesis aims to add to the current advancements in this field, specifically in the area of qubit measurements. It culminates in the implementation of a radio receiver that leverages the advantages of BiCMOS technology in cryo-environments to measure the state of a superconducting transmon-based qubit while strapped to a 4K stage in a dilution refrigerator. Critically, we demonstrate that low-noise amplification, down-conversion, and demodulation can all be done in the cryo-environment on a constrained power budget, with high fidelity comparable to a state-of-the-art (InP-HEMT LNA-based) qubit readout system, when preceded by a high-gain, quantum-noise-limited Josephson parametric amplifier.
Quantum computers hold a promise to solve intractable problems that can not be solved with classical computers. In quantum computers, information is processed in qubits as opposed to bits. The proper operation of qubits requires them to be operated in a quantum state; hence they need to be cooled down to temperatures well below l1K. Using qubits and their quantum mechanical property, quantum computers can achieve exponential speedup in solving certain computing problems compared to classical computers. However, this can only be achieved by employing thousands of qubits. At the current state of play, quantum computers are still far from practical. The current state-of-the-art solution dictates that each qubit needs multiple interconnects towards room temperature and requires bulky room temperature instruments for qubit readout and control. Clearly, this current solution will not scale well for a quantum computer with many qubits. In an effort to solve this issue, it has been proposed to realize dedicated integrated circuits for control and readout of the qubits and operate them closer to the qubits' operating temperature to enable scalability. The thesis presents the implementation of an integrated RF receiver for spin and superconducting qubit readout applications. The work aims to replace the bulky room temperature electronics with an integrated solution that operates at 4K to enable scalability and simplification of the quantum computing architecture. The receiver has been designed in the TSMC 40nm CMOS technology and has been characterized in room temperature and 4K. The measured performance shows that the receiver features a gain of 58 dB and a minimum double-sideband noise figure of 0.6 dB at 4K with an operating frequency of 6-8 GHz; a comparable performance to the current state-of-the-art room temperature electronics used for qubit readout. Moreover, this work demonstrates a qubit readout experiment with the integrated receiver in both room temperature and 4K. The qubit readout experiment shows a comparable qubit readout performance with the integrated receiver at room temperature. However, due to oscillation problems, a degradation in qubit readout performance with the chip operating at 4K is observed.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Today’s quantum computing systems rely on commercial electronics operating at room temperature in order to perform control and readout operations for qubits [1] –[6]. The qubits operate at cryogenic temperatures; the signals that support control and readout of qubits therefore traverse multiple temperature stages in a dilution refrigerator to enable interaction with the qubits of a quantum computer. For many of the most advanced quantum computers built to date, the control of each individual qubit demands application of a radiofrequency pulse that is precisely calibrated in frequency, amplitude, and phase. Oubit readout demands the amplification of very low amplitude signals that are then post-processed to categorize the state of the qubit being measured. Oubit control electronics are implemented using arbitrary waveform generators (AWGs) of various types. The scalability of such systems is challenged by the need to scale the number of qubit control electronics units linearly with the number of qubits in the system. One approach to mitigating this challenge that is under active exploration is the use of multi-channel AWGs (tailored to the requirements of qubit control) that operate at the 4K stage of a quantum computing system [7] –[10]. Oubit readout electronics are typically implemented using multiple stages of amplification and then DSP-based readout performed at room temperature. In today’s systems, while readout electronics benefits from multiplexing of the readout signals (enabling a single cascade of moderately wideband amplifiers to support the delivery of multiple readout signals to the room-temperature electronics), again, the scalability of this approach is challenged much as is the case with control electronics. One approach to mitigating the readout challenge is the expanded use of cryogenic electronics in the readout chain. Success in the implementation of cryogenic control and readout solutions depends critically on multiple CMOS sub-components; in this paper we focus on SRAM and low noise amplifiers (LNAs). Note that SRAM is critical for both control and readout applications as a mixed-signal solution involving the combination of a custom processor and analog elements is highly desirable in both cases. Further, while the LNA is directly used as an element in the readout chain, a deep assessment of LNA performance and opportunities strongly benefits overall understanding of achievable noise performance in CMOS technologies at cryogenic temperatures and is therefore impoitant in both control and readout contexts.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at 3−4K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of 10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at 3−4K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be <1mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion, 4K receiver for qubit readout that achieves >1.9GHz of IF bandwidth with >50dB conversion gain and 0.7dB NF while consuming only 17mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing 3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.