In the pursuit of quantum computing, solid-state quantum systems, particularly superconducting ones, have made remarkable advancements over the past two decades. However, achieving fault-tolerant quantum computing for next-generation applications necessitates the integration of several million qubits, which presents significant challenges in terms of interconnection complexity and latency that are currently unsolvable with state-of-the-art room-temperature control and readout electronics. Recently, cryogenic integrated circuits (ICs), including CMOS radio-frequency ICs and rapid-single-flux-quantum-logic ICs, have emerged as potential alternatives to room-temperature electronics. Unlike their room-temperature counterparts, these ICs are deployed within cryostats to enhance scalability by reducing the number and length of transmission lines. Additionally, operating at cryogenic temperatures can suppress electronic noise and improve qubit control fidelity. However, for CMOS ICs specifically, circuit design uncertainties arise due to a lack of reliable models for cryogenic field effect transistors as well as issues related to severe fickle noises and power dissipation at cryogenic temperatures. This paper provides a comprehensive review of recent research on both types of cryogenic control and readout ICs but primarily focuses on the more mature CMOS technology. The discussion encompasses principles underlying control and readout techniques employed in cryogenic CMOS ICs along with their architectural designs; characterization and modeling approaches for field effect transistors under cryogenic conditions; as well as fundamental concepts pertaining to rapid single flux quantum circuits.
In the pursuit of quantum computing, solid-state quantum systems, particularly superconducting ones, have made remarkable advancements over the past two decades. However, achieving fault-tolerant quantum computing for next-generation applications necessitates the integration of several million qubits, which presents significant challenges in terms of interconnection complexity and latency that are currently unsolvable with state-of-the-art room-temperature control and readout electronics. Recently, cryogenic integrated circuits (ICs), including CMOS radio-frequency ICs and rapid-single-flux-quantum-logic ICs, have emerged as potential alternatives to room-temperature electronics. Unlike their room-temperature counterparts, these ICs are deployed within cryostats to enhance scalability by reducing the number and length of transmission lines. Additionally, operating at cryogenic temperatures can suppress electronic noise and improve qubit control fidelity. However, for CMOS ICs specifically, circuit design uncertainties arise due to a lack of reliable models for cryogenic field effect transistors as well as issues related to severe fickle noises and power dissipation at cryogenic temperatures. This paper provides a comprehensive review of recent research on both types of cryogenic control and readout ICs but primarily focuses on the more mature CMOS technology. The discussion encompasses principles underlying control and readout techniques employed in cryogenic CMOS ICs along with their architectural designs; characterization and modeling approaches for field effect transistors under cryogenic conditions; as well as fundamental concepts pertaining to rapid single flux quantum circuits.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
This article will review recent progress in cryogenic CMOS designs for future scaled quantum computing applications. After introducing the scaling challenges associated with qubit control and readout electronics operating at room temperature, approaches taken to date to cryogenic control electronics design will be discussed, focusing on the most recent relevant publications. Elements of ultra-low power circuit and system design approaches for cryogenic controllers in scaled CMOS nodes (40nm to 14nm) will be reviewed, including a discussion of current state-of-the art cryogenic controller performance and power efficiency. Note that leading designs, when operated as transmon qubit state controllers, have achieved gate error rates in the range of 10-4 to 10-3 achieving spurious free dynamic range (SFDR) of ~40dB while consuming 4-23mW of power per qubit under active control, with power efficiency strongly driven by the complexity of the digital processor integrated in the controller design. These demonstrations, while significant, are just the first steps toward achieving the performance, efficiency, and scalability that will be required for future systems. This review article will discuss fundamental tradeoffs in CMOS cryogenic designs in order to address the needs of future scaled quantum computing systems.
Quantum computing promises an exponentially higher computational power than classical computers; although all the building blocks have become available, certain constraints still prevent quantum advantage. The fundamental challenge in building a practical quantum computer is integrating thousands of highly coherent qubits with the control and readout electronics. The need for a high‐coherence qubit drives the effort for quantum error correction algorithms to create fault‐tolerant quantum systems. Error correction becomes tangible in a quantum processor only in large numbers of qubits. Thus, the other challenge is reducing the number of physical interconnects (coaxial lines) between the quantum–classical interface and bulky room‐temperature electronics. To interface thousands of qubits, interconnects can be reduced by bringing the control and readout electronics near the quantum processor. Cryogenic complementary metal–oxide–semiconductor (CMOS) technology has been an ideal candidate for this purpose. Integrated control and readout at cryogenic temperatures require low power dissipation circuit designs and techniques such as frequency‐division multiplexing (FDM) due to the finite cooling power of a dilution refrigerator. Herein, an overview of each building block in a superconducting quantum computer is provided, focusing on scalability. Furthermore, this article is concluded with an outlook discussing current challenges and future directions for the scalable superconducting control and readout.
Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <; 100mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.
Abstract Realizing a practically useful superconducting quantum computer will require a dramatic scale-up of quantum control electronics to meet the growth in required qubit counts. Conventional rack-based room-temperature control electronics impose severe constraints on wiring density, cost, and system footprint, creating a barrier to large-scale and fault-tolerant quantum computing. Here we demonstrate a hybrid quantum control architecture that combines cryogenic complementary metal-oxide semiconductor (cryo‑CMOS) application-specific integrated circuits (ASICs) for two‑qubit flux control with room‑temperature radio‑frequency electronics for single‑qubit control and readout. The resulting system achieves high density and scalable quantum control without compromising two‑qubit gate fidelity. Deployed on a 156‑qubit quantum processor, the cryo-CMOS subsystem achieves two‑qubit gate errors at the {10}^{-3} level, with a best randomized benchmarking error per gate of 8.4\times{10}^{-4}, stable operation over multi‑day timescales, and no measurable performance degradation as we increase the temperature of the cryo-CMOS ASICs from 7 to 20 K. Thermal analysis identifies cryo-CMOS chip operation near 20 K as a favorable regime, enabling efficient cooling of a large number of channels per cryostat. Compared against rack‑based flux-control, the cryo-CMOS subsystem achieves statistically indistinguishable two-qubit gate fidelities under matched gate settings and enables a tenfold improvement in system spatial footprint. These results establish cryo‑CMOS flux control as a practical and scalable foundation for large‑scale and fault-tolerant superconducting quantum systems.