A Passive Front-End Receiver for RF Reflectometry Readout in Spin Qubits
Bagas Prabowo, Oriol Pietx-Casas, Mohammad Ali Montazerolghaem, Larysa Tryputen, Giordano Scappucci, Lieven M. K. Vandersypen, Fabio Sebastiano, Masoud Babaie
A scalable spin-qubit quantum processor requires fast, high-fidelity readout circuits operating at cryogenic temperatures (CTs). This work analyzes the radio frequency (RF) reflectometry readout mechanism to establish the link between conductance modulation, single-electron transistor (SET) matching network design, reflected signal power, and receiver (RX) noise temperature. Based on this analysis, a cryogenic RX architecture employing a passive switched-capacitor front-end is proposed. The front-end performs RF amplification and downconversion using transistors as switches, avoiding active RF amplification and mitigating shot-noise limitations. The RX is implemented in 40-nm CMOS and operates from 100 MHz to 2.2 GHz. Measurements demonstrate a minimum noise temperature of approximately 15 K at 4.2 K. When integrated with a quantum device, the RX achieves a signal-to-noise ratio (SNR) of 9.8 dB for a 10-µs integration time and enables 99.9% charge-state readout fidelity without external cryogenic amplifiers. This work represents the first demonstration of such fidelity using a cryo-CMOS RX and constitutes an important step toward scalable integration of qubit readout electronics.
A scalable spin-qubit quantum processor requires fast, high-fidelity readout circuits operating at cryogenic temperatures (CTs). This work analyzes the radio frequency (RF) reflectometry readout mechanism to establish the link between conductance modulation, single-electron transistor (SET) matching network design, reflected signal power, and receiver (RX) noise temperature. Based on this analysis, a cryogenic RX architecture employing a passive switched-capacitor front-end is proposed. The front-end performs RF amplification and downconversion using transistors as switches, avoiding active RF amplification and mitigating shot-noise limitations. The RX is implemented in 40-nm CMOS and operates from 100 MHz to 2.2 GHz. Measurements demonstrate a minimum noise temperature of approximately 15 K at 4.2 K. When integrated with a quantum device, the RX achieves a signal-to-noise ratio (SNR) of 9.8 dB for a 10-µs integration time and enables 99.9% charge-state readout fidelity without external cryogenic amplifiers. This work represents the first demonstration of such fidelity using a cryo-CMOS RX and constitutes an important step toward scalable integration of qubit readout electronics.
Currently, radio frequency (RF) measurement setups for semiconductor qubits are implemented with high performance discrete devices operating at cryogenic temperatures, and the output signals are detected by room temperature instruments.This is impractical for a real quantum processor, and integrated circuits (ICs) should be designed for spin qubit readout in a practical quantum computer, to ensure system reliability and compactness.To guide the system-level IC design, we analyze in this work noise specifications of RF front-end circuits for qubit readout, mainly focusing on noise figure (NF) of the lownoise-amplifier (LNA) and phase noise (PN) of the voltage-controlled-oscillator (VCO).RF reflectometry and RF dispersive gate sensing (DGS) are two main spin qubit readout techniques, both of which should detect weak reflected signals as low as -135 dBm and distinguish <1% amplitude or phase variation, which results in high sensitivity and low noise requirements for the readout circuits, to achieve the high measurement fidelity.For the analysis, we model the RF reflectometry and RF-DGS as demodulators respectively of the on-off keying (OOK) signal and phase modulated (PM) signal from qubits.From this, we provide a first estimation of the required NF and PN for a given fidelity and readout bandwidth, as well as an insight into the relationship between phase resolution of RF-DGS and performance degradation due to PN of the VCO.We then review some state-of-the-art CMOS LNA and VCO topologies, which can be utilized in the spin qubit readout ICs to satisfy the specifications.
Continuous rounds of quantum error correction (QEC) are essential to achieve fault-tolerant quantum computers (QCs). In each QEC cycle, thousands of ancilla quantum bits (qubits) must be read out faster than the qubits’ decoherence time (≫T2∗∼120μs for spin qubits). To address this urgent need, several CMOS receivers operating at cryogenic temperatures (cryo-CMOS RXs) have recently been introduced for gate-based [1] and RF reflectometry [2] readout of spin qubits, as well as transmons’ dispersive readout [3]. However, they have a few shortcomings. First, due to the temperature-independent shot noise of transistors in nanometer CMOS technology [4], their measured noise temperature (TN) is limited to 40K, thus degrading qubit readout fidelity. Second, due to their large TN, prior art showed either only the electrical performance of their chips by applying a relatively large (i.e., -85dBm [2]) modulated signal directly to the RX input [2, 3] or offered limited qubit measurements by exploiting a HEMT amplifier prior to the RX [1]. Those issues hinder future monolithic integration between solid-state qubits and readout electronics. This work advances the prior art by (1) introducing a wideband passive amplification circuit at the RX front-end to minimize the shot noise contribution of the active devices, lowering prior art TNby ∼2.7x; (2) demonstrating the RX performance in an RF-reflectometry qubit readout scheme without using off-the-shelf LNA prior to the RX.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at 3−4K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of 10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at 3−4K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be <1mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion, 4K receiver for qubit readout that achieves >1.9GHz of IF bandwidth with >50dB conversion gain and 0.7dB NF while consuming only 17mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing 3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
Compact and scalable quantum computer required physical qubits with low footprint and cryogenic electronics to be used in situ as standard control/readout system. The small spatial gap between the quantum chip and the cryogenic electronics limits the complexity of the wiring connections and the associated stray capacitance of the wires themselves, yielding a gain in terms of bandwidth and resolution. These improvements allow to design a fully-integrated CMOS readout based on current measurements with similar performances compared to the most common RF reflectometry-based readout technique. Here, we propose an acquisition system, operating at 4.2 K, which converts the spin dependent current coming from a single-electron transistor charge sensor into a digital output with a small power consumption (1 mW/qubit) and small occupation area (2). The system on chip consists of a low noise active integrator for the spin current, feeding a programmable threshold comparator to provide a digital output of the qubit state. It exhibits a resolution of tens of pA over an average input current of 1 nA with a time resolution of 1 μs.Compared to spin-qubit readout based on RF-reflectometry techniques, our solution does not require bulky off-chip compo-nents and to handle microwave signal and fast analog-to digital converters.
Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <; 100mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.