This paper presents a cryo-CMOS readout SoC based on a homodyne demodulation architecture with an integrating receiver. The homodyne receiver module for each qubit employs a dedicated local LO generator for a coherent detection under a frequency-division multiplexed multi-qubit readout environment. To mitigate the conventional issues of the homodyne demodulation in wireless communications, such as 1/f noise and DC offset by LO leakage, the proposed receiver incorporates effective calibration schemes by utilizing the specific operating conditions of the superconducting qubits. The implemented chip in 40 nm CMOS is tested at 4 K in a dilution refrigerator under an emulated SNR environment of superconducting qubit readout, i.e. -70 dBm input with a noise floor of -148 dBm/Hz. Measurement shows that circuit-only fidelity reaches 99% in 200 ns with an ideal single tone RF input. A back-to-back test using an on-chip 4-tone transmitter shows a 93 % circuit-only fidelity with 400 ns integration.
Superconducting qubits are promising candidates for building scalable quantum computers, but they require efficient and flexible readout systems that operate at cryogenic temperatures. This article presents a cryo-CMOS analog baseband (ABB) for superconducting qubits readout, which targets flexibly reconfigurable gain, center frequency, and bandwidth. The ABB achieves power and area reduction by integrating programmable-gain amplifiers and filters in one block and by using differential capacitors rather than single-ended ones. The differential-mode gain and common-mode stability of the low-pass filter are improved by negative-impedance inverters. Implemented in 28-nm Bulk CMOS technology, the ABB occupies an active area of 0.016 mm2. It has a tunable gain range from 10.7 to 42.5 dB, a center frequency from 101 to 189 MHz, and a bandwidth from 1.3 to 2.8 MHz. Thus, the ABB enables high-fidelity and low-power readout of superconducting qubits for future large-scale quantum computers.
This article presents a fully integrated Cryo-CMOS system on chip (SoC) for quantum computing. The proposed SoC integrates a radio frequency (RF) pulse modulator for qubit state manipulation, a multi-tone signal generator and a coherent receiver for qubit state readout, and 22 DACs for high-speed voltage pulsing of qubit gates. By adopting frequency division multiplexing and direct digital synthesis (DDS), the RF pulse modulator can control up to 16 qubits over a single RF line, and the readout receiver can detect the state of up to six qubits simultaneously. The proposed SoC also integrates a microcontroller for low latency on-chip signal processing and increased flexibility in implementing quantum instruction sets. A detailed analysis of qubit-state readout fidelity and the impact of finite DAC resolution on two-qubit gate fidelity is also included in this article, together with an electrical specification summary. The SoC is implemented in Intel’s 22 nm FFL fin field-effect transistor (FinFET) process, and it is characterized both at room and 4 K temperatures. The performance of each specific block is measured, with the readout characterized in a loop-back configuration. Generation of the control signals required for a full Rabi oscillation experiment is also demonstrated. This article also describes the cryogenic thermalization techniques used to integrate the SoC in the dilution refrigerator and shows temperature measurements during operation.
Millions of qubits need to be employed in a quantum computer to achieve a fault-tolerant quantum operation. To reduce the complexity in such a large-scale system, the control and readout circuitries have been proposed to be placed at the 4 K stage of dilution refrigerators [1]. CMOS technology is commonly used to leverage its scaling to enable large integration of control and readout circuitries with qubits. However, the high-fidelity readout operations require low noise amplifiers (LNAs) with a noise temperature of a few Kelvins. This necessitates the usage of HEMT and parametric amplifiers [2]. Recently reported CMOS LNAs are still far away from attaining such good performance [3–5]. Thus, this is one of the greatest challenges on the way to the fully integrated CMOS readout. Additionally, due to the limited cooling power of dilution refrigerators, low-power solutions are needed for achieving a very good noise performance at 4 K. This paper presents a 28 nm CMOS LNA for qubit readout, which achieves an order of magnitude power reduction compared to its CMOS counterparts while still providing a similar good noise Figure (NF) performance at 4 K.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at
3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of
10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at
3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be
<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion,
4 K receiver for qubit readout that achieves
>1.9GHz of IF bandwidth with
>50 dB conversion gain and
0.7 dB NF while consuming only
17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing
3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
In quantum computers, the quantum state discrimination of the physical quantum bits (Qubits) occupies ~80% of the quantum error correction (QEC) cycle. The RF reflectometry or dispersive readout determines the Qubit state by monitoring the RF reflection of the attached high-Q resonant tank. Compared to their dc counterparts, the RF reflectometers enjoy a high signal-to-noise ratio (SNR), low drifting, and fast speed. As a result, a high-fidelity, single-shot, scalable reflectometer array based on cryogenic CMOS (Cryo-CMOS) ICs is in demand for the future large-scale Qubit array (
103∼106Qubits). However, the classic Cryo-CMOS heterodyne reflectometers, consisting of MOSFET-based LNA, mixer, and baseband blocks, suffer from high noise temperature and dc power. To address these issues, the Cryo-CMOS parametric circuitry based on varactors is explored. In this article, a dual-Qubit homodyne reflectometer array with 2 RX channels and 1 TX channel is demonstrated. In the RX, the degenerate parametric amplifier (DPA) enjoys a Q-enhanced,
λRF/2differential-mode (DM) resonator for the high-gain parametric amplification. The common mode (CM) RF input of DPA interacts with the DM resonator by a nonreciprocal, dynamic mode coupling (DMC). It eliminates the necessity of a circulator and the potential oscillation of DPA. The scalability challenge of the DPA’s noise temperature
Tnoiseversus the environment temperature
Tenvis also investigated. In the TX, a current-mode logic (CML) divider with interstate locking and a vector modulator (VM) is implemented to achieve fast modulation for the spur and noise rejection. Measured at 4.2 K, the implemented 65 nm Cryo-CMOS chip presents a
4.5∼7GHz bandwidth, 52 dB peak RF gain, and 78 K noise temperature, and generates a 10 MHz TX pulse train with -22 dBm RF power and 30 dB tunability. It consumes a total dc power of 33 mW.