Superconducting qubits are promising candidates for building scalable quantum computers, but they require efficient and flexible readout systems that operate at cryogenic temperatures. This article presents a cryo-CMOS analog baseband (ABB) for superconducting qubits readout, which targets flexibly reconfigurable gain, center frequency, and bandwidth. The ABB achieves power and area reduction by integrating programmable-gain amplifiers and filters in one block and by using differential capacitors rather than single-ended ones. The differential-mode gain and common-mode stability of the low-pass filter are improved by negative-impedance inverters. Implemented in 28-nm Bulk CMOS technology, the ABB occupies an active area of 0.016 mm2. It has a tunable gain range from 10.7 to 42.5 dB, a center frequency from 101 to 189 MHz, and a bandwidth from 1.3 to 2.8 MHz. Thus, the ABB enables high-fidelity and low-power readout of superconducting qubits for future large-scale quantum computers.
Superconducting qubits are promising candidates for building scalable quantum computers, but they require efficient and flexible readout systems that operate at cryogenic temperatures. This article presents a cryo-CMOS analog baseband (ABB) for superconducting qubits readout, which targets flexibly reconfigurable gain, center frequency, and bandwidth. The ABB achieves power and area reduction by integrating programmable-gain amplifiers and filters in one block and by using differential capacitors rather than single-ended ones. The differential-mode gain and common-mode stability of the low-pass filter are improved by negative-impedance inverters. Implemented in 28-nm Bulk CMOS technology, the ABB occupies an active area of 0.016 mm2. It has a tunable gain range from 10.7 to 42.5 dB, a center frequency from 101 to 189 MHz, and a bandwidth from 1.3 to 2.8 MHz. Thus, the ABB enables high-fidelity and low-power readout of superconducting qubits for future large-scale quantum computers.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit state by detecting the phase difference between the stimulus signal and the reflected signal. A low-IF N-path filter-based receiver and a multi-tone transmitter are co-designed to enable frequency-division multiplexing (FDM) dispersive readout of multiple qubits. A phase-shifter-based polar-modulation XY-driver is developed with support for fast phase quantum gate operation and derivative-removal-by-adiabatic-gate (DRAG) pulse generation. The Z-driver is realized using a static digital-to-analog converter (DAC) array and a 10-bit dynamic DAC for power efficiency. Fabricated in a 28-nm bulk CMOS process, the chipset occupies a die area of 4.6 mm2. The readout RX achieves a noise temperature of 40 K with a gain of 45–83 dB and a bandwidth of 1.2 GHz. The readout RX consumes 32% less power than state-of-the-art designs. The measured total readout power for simultaneous detection of two qubits is 12.2 mW, which is the lowest among readouts with a similar integration level. In addition, the controller achieves a spurious-free dynamic range (SFDR) of 49 dB for a 1-GS/s Z-driver and an SNR of 42 dB for a 1-GS/s XY-driver. The XY-driver consumes 4.3 mW per qubit under active control. Verified with practical transmon qubits, the readout fidelity exceeds 92.6%, approaching that of commercial instruments. A Rabi experiment at 5.61/6.36 MHz, a Ramsey experiment at 4.1 MHz, and a T1 experiment at9.98μs are also successfully observed using the proposed chipset at 3.5 K.
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at 3−4K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of 10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at 3−4K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be <1mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion, 4K receiver for qubit readout that achieves >1.9GHz of IF bandwidth with >50dB conversion gain and 0.7dB NF while consuming only 17mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing 3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
While large-scale fault-tolerant quantum computers promise to enable the solution to certain classes of problems for which no other efficient approach is known, such a machine is believed to require over a million performant qubits. Scaling today's 0(100) qubit superconducting (SC) quantum computers to this extent while also improving performance carries many daunting challenges, including control of such a large quantum processor (QP). Integrating the control electronics at an intermediate temperature stage within the cryostat is an attractive option, e.g., due to the inherent thermal stability of the cryogenic environment and the feasibility of connecting to the QP via dense low-loss/high-thermal-isolation SC lines [1], [2]. Several cryo-CMOS quantum controllers have been reported, with examples used to control spin [3] and transmon [1], [2] qubits. To date, IC-based quantum control experiments have focused on resonant RF control, but baseband signals are often central to the execution of gates. Here, we report the design and system characterization of a cryo-CMOS IC for generating both the RF and baseband signals required for full control of a SC QP unit-cell, and show its ability to implement the components of a high-fidelity gate set that is universal for quantum computing.
This paper presents the design and test results of a CMOS current-based Digital to Analog Converter (DAC) that operates at cryogenic temperatures and that can be used to precisely control the amount of flux coupled to qubits or that can be used in the readout of superconducting circuits. The current pulse output can be controlled in terms of its amplitude, rise and fall slopes, via digital controls, and pulse width, via external triggers, while driving a superconducting circuit. The design has been implemented in a planar 90 nm CMOS process and test results closely match circuit predictions. The solution's wide degree of digital tunability affords potential application of the same device to many types of quantum circuits, beyond those discussed here. Due to the wide-ranging flexibility of digital CMOS control, we envision that this DAC design will enable the next generation of high-fidelity cryo-CMOS control architectures for superconducting qubits.