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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

34.2 A 28-nm Bulk-CMOS IC for Full Control of a Superconducting Quantum Processor Unit-Cell

Juhwan Yoo, Zijun Chen, Frank Arute, Shirin Montazeri, Marco Szalay, Catherine Erickson, Evan R. Jeffrey, Reza Fatemi, Marissa Giustina, M. Ansmann, Erik A. Lucero, J. Kelly, Joseph C. Bardin

Published Feb 19, 2023• 37 citations
Publisher

Abstract

While large-scale fault-tolerant quantum computers promise to enable the solution to certain classes of problems for which no other efficient approach is known, such a machine is believed to require over a million performant qubits. Scaling today's 0(100) qubit superconducting (SC) quantum computers to this extent while also improving performance carries many daunting challenges, including control of such a large quantum processor (QP). Integrating the control electronics at an intermediate temperature stage within the cryostat is an attractive option, e.g., due to the inherent thermal stability of the cryogenic environment and the feasibility of connecting to the QP via dense low-loss/high-thermal-isolation SC lines [1], [2]. Several cryo-CMOS quantum controllers have been reported, with examples used to control spin [3] and transmon [1], [2] qubits. To date, IC-based quantum control experiments have focused on resonant RF control, but baseband signals are often central to the execution of gates. Here, we report the design and system characterization of a cryo-CMOS IC for generating both the RF and baseband signals required for full control of a SC QP unit-cell, and show its ability to implement the components of a high-fidelity gate set that is universal for quantum computing.

DOI
10.1109/isscc42615.2023.10067292

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IEEE Journal of Solid-State Circuits•Oct 11, 2019•177 citations
While large-scale fault-tolerant quantum computers promise to enable the solution to certain classes of problems for which no other efficient approach is known, such a machine is believed to require over a million performant qubits. Scaling today's 0(100) qubit superconducting (SC) quantum computers to this extent while also improving performance carries many daunting challenges, including control of such a large quantum processor (QP). Integrating the control electronics at an intermediate temperature stage within the cryostat is an attractive option, e.g., due to the inherent thermal stability of the cryogenic environment and the feasibility of connecting to the QP via dense low-loss/high-thermal-isolation SC lines [1], [2]. Several cryo-CMOS quantum controllers have been reported, with examples used to control spin [3] and transmon [1], [2] qubits. To date, IC-based quantum control experiments have focused on resonant RF control, but baseband signals are often central to the execution of gates. Here, we report the design and system characterization of a cryo-CMOS IC for generating both the RF and baseband signals required for full control of a SC QP unit-cell, and show its ability to implement the components of a high-fidelity gate set that is universal for quantum computing.
A universal fault-tolerant quantum computer will require large-scale control systems that can realize all the waveforms required to implement a gateset that is universal for quantum computing. Optimization of such a system, which must be precise and extensible, is an open research challenge. Here, we present a cryogenic quantum control integrated circuit (IC) that is able to control all the necessary degrees of freedom of a two-qubit subcircuit of a superconducting quantum processor. Specifically, the IC contains a pair of 4–8-GHz RF pulse generators forXYXYXYcontrol, three baseband current generators for qubit and coupler frequency control, and a digital controller that includes a sequencer for gate sequence playback. After motivating the architecture, we describe the circuit-level implementation details and present experimental results. Using standard benchmarking techniques, we show that the cryogenic CMOS (cryo-CMOS) IC is able to execute the components of a gateset that is universal for quantum computing while achieving single-qubitXYXYXYandZZZaverage gate error rates of 0.17%–0.36% and 0.14%–0.17%, respectively, as well as two-qubit average cross-entropy benchmarking (XEB) cycle error rates of 1.2%. These error rates, which were achieved while dissipating just 4 mW/qubit, are comparable to the measured error rates obtained using baseline room-temperature electronics.
Abstract Realizing a practically useful superconducting quantum computer will require a dramatic scale-up of quantum control electronics to meet the growth in required qubit counts. Conventional rack-based room-temperature control electronics impose severe constraints on wiring density, cost, and system footprint, creating a barrier to large-scale and fault-tolerant quantum computing. Here we demonstrate a hybrid quantum control architecture that combines cryogenic complementary metal-oxide semiconductor (cryo‑CMOS) application-specific integrated circuits (ASICs) for two‑qubit flux control with room‑temperature radio‑frequency electronics for single‑qubit control and readout. The resulting system achieves high density and scalable quantum control without compromising two‑qubit gate fidelity. Deployed on a 156‑qubit quantum processor, the cryo-CMOS subsystem achieves two‑qubit gate errors at the {10}^{-3} level, with a best randomized benchmarking error per gate of 8.4\times{10}^{-4}, stable operation over multi‑day timescales, and no measurable performance degradation as we increase the temperature of the cryo-CMOS ASICs from 7 to 20 K. Thermal analysis identifies cryo-CMOS chip operation near 20 K as a favorable regime, enabling efficient cooling of a large number of channels per cryostat. Compared against rack‑based flux-control, the cryo-CMOS subsystem achieves statistically indistinguishable two-qubit gate fidelities under matched gate settings and enables a tenfold improvement in system spatial footprint. These results establish cryo‑CMOS flux control as a practical and scalable foundation for large‑scale and fault-tolerant superconducting quantum systems.
While quantum processors are typically cooled to1,000 physical qubits will be required to encode one error-corrected qubit [1]. Implementing a system with 1,000 error-corrected qubits will likely require moving from the contemporary paradigm where control and readout of the quantum processor is carried out using racks of room temperature electronics to one in which integrated control/readout circuits are located within the cryogenic environment and connected to the quantum processor through superconducting interconnects [2]. This is a major challenge, as the cryo ICs must be high performance and very low power (eventually <; 1 mW/qubit). In this paper, we report the design and system-level characterization of a prototype cryo-CMOS IC for performing XY gate operations on transmon (XMON) qubits.
Quantum computing promises exponential speed-up in solving certain complex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I/Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a μ\muμ-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.
A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3digitally controlled oscillator required to manipulate the state of qubits.
Implementation of an error-corrected quantum computer is believed to require a quantum processor with a million or more physical qubits, and, in order to run such a processor, a quantum control system of similar scale will be required. Such a controller will need to be integrated within the cryogenic system and in close proximity with the quantum processor in order to make such a system practical. Here, we present a prototype cryogenic CMOS quantum controller designed in a 28-nm bulk CMOS process and optimized to implement a 16-word (4-bit)XYgate instruction set for controlling transmon qubits. After introducing the transmon qubit, including a discussion of how it is controlled, design considerations are discussed, with an emphasis on error rates and scalability. The circuit design is then discussed. Cryogenic performance of the underlying technology is presented, and the results of several quantum control experiments carried out using the integrated controller are described. This article ends with a comparison to the state of the art and a discussion of further research to be carried out. It has been shown that the quantum control IC achieves promising performance while dissipating less than 2 mW of total ac and dc power and requiring a digital data stream of less than 500 Mb/s.