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Geometric Limits of Surface Loss in Transmon Wiring: Analytical Framework and Design Rules

A. R Hossain, Tanu Arefin

Published Apr 22, 2026• 0 citations
Publisher

Abstract

Dielectric surface loss from junction wiring represents a critical secondary limit for superconducting transmon coherence. We present a quasi-one-dimensional analytical framework to minimise this loss, enabling rapid optimisation without computationally expensive 3D simulations. We compare uniform strips (V1) against linear (V2–V3) and optimised hybrid tapers (V4–V5). We demonstrate that geometric tapering suppresses wiring participation by up to 99.6%, reducing it from 0.0756 ppm (V1) to 0.0003 ppm (V4). Crucially, however, a simple linear taper (T1 ≈ 127.306 μs) yields coherence virtually indistinguishable from theoretically optimal complex profiles (T1 ≈ 127.323 μs) in the current pad-dominated regime. We thus establish a definitive design rule: standard linear tapering is sufficient to eliminate wiring loss as a bottleneck, rendering fabrication-sensitive complex shapes unnecessary for next-generation, low-loss devices.

DOI
10.20944/preprints202604.1559.v1

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Dielectric surface loss from junction wiring represents a critical secondary limit for superconducting transmon coherence. We present a quasi-one-dimensional analytical framework to minimise this loss, enabling rapid optimisation without computationally expensive 3D simulations. We compare uniform strips (V1) against linear (V2–V3) and optimised hybrid tapers (V4–V5). We demonstrate that geometric tapering suppresses wiring participation by up to 99.6%, reducing it from 0.0756 ppm (V1) to 0.0003 ppm (V4). Crucially, however, a simple linear taper (T1 ≈ 127.306 μs) yields coherence virtually indistinguishable from theoretically optimal complex profiles (T1 ≈ 127.323 μs) in the current pad-dominated regime. We thus establish a definitive design rule: standard linear tapering is sufficient to eliminate wiring loss as a bottleneck, rendering fabrication-sensitive complex shapes unnecessary for next-generation, low-loss devices.
Abstract Surface dielectric loss from superconducting transmon qubits is believed to be one of the dominant sources of decoherence. Reducing surface dielectric loss is crucial for achieving a high quality factor and a long relaxation time (T 1), which can be engineered by carefully changing the geometry of a transmon. In this paper, we present a shape-optimization approach to reduce surface dielectric loss in a transmon qubit. The capacitor pads and junction wires of transmons are shaped as spline curves and optimized through the finite-element method and a global optimization algorithm. We find that the participation ratio of capacitor pads and junction wires can be reduced by 15 % − 18 % and 22 % − 26 % compared to previous designs, while the overall footprint and anharmonicity are maintained at acceptable values. As a result, the two-level system-limited quality factor and the corresponding T 1 were increased by 21.6%.
Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.
Abstract Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
Dielectric loss from different interfacial layers in the superconducting circuit and from external environment may cause superconducting qubit decoherence. Compared to modeling the entire device at once with a numerical solver, quantitatively formulating the dielectric loss can both describe all loss mechanisms and make the optimization more transparent. In this paper, we first analyze the expression formula of dielectric loss, and obtain a design scheme that can reduce the dielectric loss of qubits. That is, we replace the straight junction wires with the tapered junction wires. Based on this scheme, we perform a simulation to optimize the design of junction wires. Finally, a real experiment is conducted to verify our design. The results show that both the T1 time and T2 time of qubits are significantly improved.
We study the energy relaxation times (T1) of superconducting transmon qubits in 3D cavities as a function of dielectric participation ratios of material surfaces. This surface participation ratio, representing the fraction of electric field energy stored in a dissipative surface layer, is computed by a two-step finite-element simulation and experimentally varied by qubit geometry. With a clean electromagnetic environment and suppressed non-equilibrium quasiparticle density, we find an approximately proportional relation between the transmon relaxation rates and surface participation ratios. These results suggest dielectric dissipation arising from material interfaces is the major limiting factor for the T1 of transmons in 3D circuit quantum electrodynamics architecture. Our analysis also supports the notion of spatial discreteness of surface dielectric dissipation.