Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Entropy

Suppressing the Dielectric Loss in Superconducting Qubits through Useful Geometry Design

Haoran He, Weilong Wang, Fudong Liu, Benzheng Yuan, Zheng Shan

Published Jul 8, 2022• 9 citations
Publisher

Abstract

Dielectric loss from different interfacial layers in the superconducting circuit and from external environment may cause superconducting qubit decoherence. Compared to modeling the entire device at once with a numerical solver, quantitatively formulating the dielectric loss can both describe all loss mechanisms and make the optimization more transparent. In this paper, we first analyze the expression formula of dielectric loss, and obtain a design scheme that can reduce the dielectric loss of qubits. That is, we replace the straight junction wires with the tapered junction wires. Based on this scheme, we perform a simulation to optimize the design of junction wires. Finally, a real experiment is conducted to verify our design. The results show that both the T1 time and T2 time of qubits are significantly improved.

DOI
10.3390/e24070952

Related papers

Shape optimization of superconducting transmon qubits for low surface dielectric loss

Sungjun Eun, Seong Hyeon Park, Kyungsik Seo +2 more

Abstract Surface dielectric loss from superconducting transmon qubits is believed to be one of the dominant sources of decoherence. Reducing surface dielectric loss is crucial for achieving a high quality factor and a long relaxation time (T 1), which can be engineered by carefully changing the geometry of a transmon. In this paper, we present a shape-optimization approach to reduce surface dielectric loss in a transmon qubit. The capacitor pads and junction wires of transmons are shaped as spline curves and optimized through the finite-element method and a global optimization algorithm. We find that the participation ratio of capacitor pads and junction wires can be reduced by 15 % − 18 % and 22 % − 26 % compared to previous designs, while the overall footprint and anharmonicity are maintained at acceptable values. As a result, the two-level system-limited quality factor and the corresponding T 1 were increased by 21.6%.

arXiv:2211.14159•Journal of Physics D Applied Physics•Sep 8, 2023•12 citations

Surface loss calculations and design of a superconducting transmon qubit with tapered wiring

John M. Martinis

Abstract Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.

npj Quantum Information•Mar 7, 2022•27 citations

Optimal design of a superconducting transmon qubit with tapered wiring

John M. Martinis

Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.

arXiv:2104.01544•Apr 4, 2021•4 citations

Precise 2D electric field density simulations for superconducting quantum devices

Zydrunas Gimbutas, Wei-Ren Syong, Nhi Nguyen +5 more

Dielectric loss due to two-level systems is a limiting factor for superconducting qubit relaxation times. These losses arise mostly from nanometer-scale interfacial defect regions in superconducting devices with planar dimensions of microns to millimeters, thus making it resource intensive to accurately simulate the electric field density in these regions with traditional electromagnetic solvers. In this work, we demonstrate a fast boundary integral equation solver that allows precise simulation of electric field density in these thin regions, showing a speedup of around two orders of magnitude over traditional solvers, with relative errors around $10^{-7}$ for a ten-minute solution runtime. By computing participation ratios through Green's first identity without squaring the electric field, our approach is less susceptible to the field singularities near conductor corners. We apply this solver to a basic untrenched coplanar waveguide cross-section, showing that the common assumption of participation ratio linearity with dielectric constant holds well for some interfaces and not others; in particular, while the metal-air (MA) top and corner follow this linear relationship strongly, the MA sidewall does not. We then compare isotropic and anisotropic etching, showing that the MA sidewall and the metal-air-substrate triple junction are the most strongly affected. We are currently leveraging this solver to explore geometries that will uniquely isolate the participation ratios of the different dielectrics. Finally, we are working to combine this solver framework with a full 3D microwave solver to accurately calculate participation ratios for the thin dielectrics that are known sources of loss in superconducting qubits.

quant-pharXiv:2607.26242•Jul 30, 2026•0 citations

Wiring surface loss of a superconducting transmon qubit

Nikita S. Smirnov, Elizaveta A. Krivko, Anastasiya A. Solovyova +2 more

Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.

arXiv:2311.16794•Scientific Reports•Mar 27, 2024•18 citations

Decoherence in Josephson Qubits from Dielectric Loss

John M. Martinis, Ken B. Cooper, R. McDermott +8 more

Dielectric loss from two-level states is shown to be a dominant decoherence source in superconducting quantum bits. Depending on the qubit design, dielectric loss from insulating materials or the tunnel junction can lead to short coherence times. We show that a variety of microwave and qubit measurements are well modeled by loss from resonant absorption of two-level defects. Our results demonstrate that this loss can be significantly reduced by using better dielectrics and fabricating junctions of small area . With a redesigned phase qubit employing low-loss dielectrics, the energy relaxation rate has been improved by a factor of 20, opening up the possibility of multiqubit gates and algorithms.

arXiv:cond-mat/0507622•Physical Review Letters•Nov 16, 2005•834 citations
Dielectric loss from different interfacial layers in the superconducting circuit and from external environment may cause superconducting qubit decoherence. Compared to modeling the entire device at once with a numerical solver, quantitatively formulating the dielectric loss can both describe all loss mechanisms and make the optimization more transparent. In this paper, we first analyze the expression formula of dielectric loss, and obtain a design scheme that can reduce the dielectric loss of qubits. That is, we replace the straight junction wires with the tapered junction wires. Based on this scheme, we perform a simulation to optimize the design of junction wires. Finally, a real experiment is conducted to verify our design. The results show that both the T1 time and T2 time of qubits are significantly improved.
Abstract Surface dielectric loss from superconducting transmon qubits is believed to be one of the dominant sources of decoherence. Reducing surface dielectric loss is crucial for achieving a high quality factor and a long relaxation time (T 1), which can be engineered by carefully changing the geometry of a transmon. In this paper, we present a shape-optimization approach to reduce surface dielectric loss in a transmon qubit. The capacitor pads and junction wires of transmons are shaped as spline curves and optimized through the finite-element method and a global optimization algorithm. We find that the participation ratio of capacitor pads and junction wires can be reduced by 15 % − 18 % and 22 % − 26 % compared to previous designs, while the overall footprint and anharmonicity are maintained at acceptable values. As a result, the two-level system-limited quality factor and the corresponding T 1 were increased by 21.6%.
Abstract Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
Dielectric loss due to two-level systems is a limiting factor for superconducting qubit relaxation times. These losses arise mostly from nanometer-scale interfacial defect regions in superconducting devices with planar dimensions of microns to millimeters, thus making it resource intensive to accurately simulate the electric field density in these regions with traditional electromagnetic solvers. In this work, we demonstrate a fast boundary integral equation solver that allows precise simulation of electric field density in these thin regions, showing a speedup of around two orders of magnitude over traditional solvers, with relative errors around 10−710^{-7}10−7 for a ten-minute solution runtime. By computing participation ratios through Green's first identity without squaring the electric field, our approach is less susceptible to the field singularities near conductor corners. We apply this solver to a basic untrenched coplanar waveguide cross-section, showing that the common assumption of participation ratio linearity with dielectric constant holds well for some interfaces and not others; in particular, while the metal-air (MA) top and corner follow this linear relationship strongly, the MA sidewall does not. We then compare isotropic and anisotropic etching, showing that the MA sidewall and the metal-air-substrate triple junction are the most strongly affected. We are currently leveraging this solver to explore geometries that will uniquely isolate the participation ratios of the different dielectrics. Finally, we are working to combine this solver framework with a full 3D microwave solver to accurately calculate participation ratios for the thin dielectrics that are known sources of loss in superconducting qubits.
Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.
Dielectric loss from two-level states is shown to be a dominant decoherence source in superconducting quantum bits. Depending on the qubit design, dielectric loss from insulating materials or the tunnel junction can lead to short coherence times. We show that a variety of microwave and qubit measurements are well modeled by loss from resonant absorption of two-level defects. Our results demonstrate that this loss can be significantly reduced by using better dielectrics and fabricating junctions of small area . With a redesigned phase qubit employing low-loss dielectrics, the energy relaxation rate has been improved by a factor of 20, opening up the possibility of multiqubit gates and algorithms.