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arXiv:2211.14159 · Journal of Physics D Applied Physics

Shape optimization of superconducting transmon qubits for low surface dielectric loss

Sungjun Eun, Seong Hyeon Park, Kyungsik Seo, Kibum Choi, Seungyong Hahn

Published Sep 8, 2023• 12 citations
arXivHTMLPDF

Abstract

Abstract Surface dielectric loss from superconducting transmon qubits is believed to be one of the dominant sources of decoherence. Reducing surface dielectric loss is crucial for achieving a high quality factor and a long relaxation time (T 1), which can be engineered by carefully changing the geometry of a transmon. In this paper, we present a shape-optimization approach to reduce surface dielectric loss in a transmon qubit. The capacitor pads and junction wires of transmons are shaped as spline curves and optimized through the finite-element method and a global optimization algorithm. We find that the participation ratio of capacitor pads and junction wires can be reduced by 15 % − 18 % and 22 % − 26 % compared to previous designs, while the overall footprint and anharmonicity are maintained at acceptable values. As a result, the two-level system-limited quality factor and the corresponding T 1 were increased by 21.6%.

DOI
10.1088/1361-6463/acf7cf

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Abstract Surface dielectric loss from superconducting transmon qubits is believed to be one of the dominant sources of decoherence. Reducing surface dielectric loss is crucial for achieving a high quality factor and a long relaxation time (T 1), which can be engineered by carefully changing the geometry of a transmon. In this paper, we present a shape-optimization approach to reduce surface dielectric loss in a transmon qubit. The capacitor pads and junction wires of transmons are shaped as spline curves and optimized through the finite-element method and a global optimization algorithm. We find that the participation ratio of capacitor pads and junction wires can be reduced by 15 % − 18 % and 22 % − 26 % compared to previous designs, while the overall footprint and anharmonicity are maintained at acceptable values. As a result, the two-level system-limited quality factor and the corresponding T 1 were increased by 21.6%.
Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.
State-of-the-art transmon qubits rely on large capacitors which systematically improves their coherence due to reduced surface loss participation. However, this approach increases both the footprint and the parasitic cross-coupling and is ultimately limited by radiation losses - a potential roadblock for scaling up quantum processors to millions of qubits. In this work we present transmon qubits with sizes as low as 36$ \times 393939 μmmm^2$ with $\gtrsim$100 nm wide vacuum gap capacitors that are micro-machined from commercial silicon-on-insulator wafers and shadow evaporated with aluminum. After the release in HF vapor we achieve a vacuum participation ratio up to 99.6\% in an in-plane design that is compatible with standard coplanar circuits. Qubit relaxation time measurements for small gaps with high vacuum electric fields of up to 22 V/m reveal a double exponential decay indicating comparably strong coupling to long-lived two-level-systems (TLS). The exceptionally high selectivity of $>$20 dB to the superconductor-vacuum surface allows to precisely back out the sub-single-photon dielectric loss tangent of aluminum oxide exposed to ambient conditions. In terms of future scaling potential we achieve a qubit quality factor by footprint area of 20μs−220 μ\mathrm{s}^{-2}20μs−2, which is on par with the highest T1T_1T1​ devices relying on larger geometries and expected to improve substantially for lower loss superconductors like NbTiN, TiN or Ta.
State-of-the-art transmon qubits rely on large capacitors, which systematically improve their coherence due to reduced surface-loss participation. However, this approach increases both the footprint and the parasitic cross-coupling and is ultimately limited by radiation losses---a potential roadblock for scaling up quantum processors to millions of qubits. In this work we present transmon qubits with sizes as low as $36\phantom{\rule{0.2em}{0ex}}\ifmmode\times\else\texttimes\fi{}\phantom{\rule{0.2em}{0ex}}39\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{2}$ with $\ensuremath{\gtrsim}100$-nm-wide vacuum-gap capacitors that are micromachined from commercial silicon-on-insulator wafers and shadow evaporated with aluminum. We achieve a vacuum participation ratio up to 99.6% in an in-plane design that is compatible with standard coplanar circuits. Qubit relaxation-time measurements for small gaps with high zero-point electric field variance of up to 22 V/m reveal a double exponential decay indicating comparably strong qubit interaction with long-lived two-level systems. The exceptionally high selectivity of up to 20 dB to the superconductor-vacuum interface allows us to precisely back out the sub-single-photon dielectric loss tangent of aluminum oxide previously exposed to ambient conditions. In terms of future scaling potential, we achieve a ratio of qubit quality factor to a footprint area equal to $20\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{\ensuremath{-}2}$, which is comparable with the highest T1{T}_{1}T1​ devices relying on larger geometries, a value that could improve substantially for lower surface-loss superconductors.
Abstract Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
We study the energy relaxation times (T1) of superconducting transmon qubits in 3D cavities as a function of dielectric participation ratios of material surfaces. This surface participation ratio, representing the fraction of electric field energy stored in a dissipative surface layer, is computed by a two-step finite-element simulation and experimentally varied by qubit geometry. With a clean electromagnetic environment and suppressed non-equilibrium quasiparticle density, we find an approximately proportional relation between the transmon relaxation rates and surface participation ratios. These results suggest dielectric dissipation arising from material interfaces is the major limiting factor for the T1 of transmons in 3D circuit quantum electrodynamics architecture. Our analysis also supports the notion of spatial discreteness of surface dielectric dissipation.
Dielectric loss is one of the major decoherence sources of superconducting qubits. Contemporary high-coherence superconducting qubits are formed by material systems mostly consisting of superconducting films on substrate with low dielectric loss, where the loss mainly originates from the surfaces and interfaces. Among the multiple candidates for material systems, a combination of titanium nitride (TiN\mathrm{Ti}\mathrm{N}TiN) film and sapphire substrate has good potential because of its chemical stability against oxidization and its high quality at interfaces. In this work, we report a TiN\mathrm{Ti}\mathrm{N}TiN film deposited onto sapphire substrate achieving low dielectric loss at the material interface. Through the systematic characterizations of a series of transmon qubits fabricated with identical batches of TiN\mathrm{Ti}\mathrm{N}TiN base layers but different geometries of qubit shunting capacitors with various participation ratios of the material interface, we quantitatively extract the loss-tangent value at the substrate-metal interface, which is smaller than $8.9\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}4}$ in a 1-nm disordered layer, and a limiting quality factor of about 7.3 million. By optimizing the interface participation ratio of the two-dimensional (2D) transmon qubit, we reproducibly achieve a quality factor of 5.7 million on average. The best 2D qubits show lifetimes of up to $300\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$ and quality factors achieving 8.1 million. We demonstrate that TiN\mathrm{Ti}\mathrm{N}TiN film on sapphire substrate is an ideal material system for high-coherence superconducting qubits. Our analyses further suggest that the interface dielectric loss around the Josephson-junction part of the circuit could be the dominant limitation of lifetimes for state-of-the-art transmon qubits.