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arXiv:2311.16794 · Scientific Reports

Wiring surface loss of a superconducting transmon qubit

Nikita S. Smirnov, Elizaveta A. Krivko, Anastasiya A. Solovyova, Аnton I. Ivanov, Ilya A. Rodionov

Published Mar 27, 2024• 18 citations
arXivHTMLPDF

Abstract

Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.

DOI
10.1038/s41598-024-57248-y

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Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.
Abstract Surface dielectric loss from superconducting transmon qubits is believed to be one of the dominant sources of decoherence. Reducing surface dielectric loss is crucial for achieving a high quality factor and a long relaxation time (T 1), which can be engineered by carefully changing the geometry of a transmon. In this paper, we present a shape-optimization approach to reduce surface dielectric loss in a transmon qubit. The capacitor pads and junction wires of transmons are shaped as spline curves and optimized through the finite-element method and a global optimization algorithm. We find that the participation ratio of capacitor pads and junction wires can be reduced by 15 % − 18 % and 22 % − 26 % compared to previous designs, while the overall footprint and anharmonicity are maintained at acceptable values. As a result, the two-level system-limited quality factor and the corresponding T 1 were increased by 21.6%.
Abstract Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
Recent advances in design and fabrication have increased the energy-relaxation times of isolated superconducting transmon qubits to the hundreds-of-microseconds regime, with reported values exceeding 500 μμμs. However, the same progress has not automatically translated to multiqubit processors, where qubits are embedded in connected qubit-coupler lattices and often exhibit much shorter lifetimes than isolated qubits. To identify possible sources of this discrepancy, here we use finite-element simulation to investigate how surface participation ratios and the resulting surface dielectric loss change when a qubit is embedded in a flip-chip qubit-coupler lattice. Controlled comparisons show that higher connectivity can indeed lead to larger surface loss: in the simulated lattice, connecting a qubit to two and four couplers increases the surface loss by factors of 1.3 and 1.8, respectively. We attribute this change to the combined effects of added edge fields from coupling claws, field redistribution over the larger connected metal network, and hybridization with coupler modes. We further examine how this connectivity-induced surface-loss penalty depends on the geometric design parameters of both the qubit electrodes and the coupling claws, and derive guidelines for designing low-loss multiqubit processors.
Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.
Josephson junctions form the essential non-linearity for almost all superconducting qubits. The junction is formed when two superconducting electrodes come within ∼1 nm of each other. Although the capacitance of these electrodes is a small fraction of the total qubit capacitance, the nearby electric fields are more concentrated in dielectric surfaces and can contribute substantially to the total dissipation. We have developed a technique to experimentally investigate the effect of these electrodes on the quality of superconducting devices. We use λ/4 coplanar waveguide resonators to emulate lumped qubit capacitors. We add a variable number of these electrodes to the capacitive end of these resonators and measure how the additional loss scales with the number of electrodes. We then reduce this loss with fabrication techniques that limit the amount of lossy dielectrics. We then use these techniques for the fabrication of Xmon qubits on a silicon substrate to improve their energy relaxation times by a factor of 5.
We study the energy relaxation times (T1) of superconducting transmon qubits in 3D cavities as a function of dielectric participation ratios of material surfaces. This surface participation ratio, representing the fraction of electric field energy stored in a dissipative surface layer, is computed by a two-step finite-element simulation and experimentally varied by qubit geometry. With a clean electromagnetic environment and suppressed non-equilibrium quasiparticle density, we find an approximately proportional relation between the transmon relaxation rates and surface participation ratios. These results suggest dielectric dissipation arising from material interfaces is the major limiting factor for the T1 of transmons in 3D circuit quantum electrodynamics architecture. Our analysis also supports the notion of spatial discreteness of surface dielectric dissipation.