Connectivity-induced surface-loss penalty in superconducting qubit-coupler lattices

Abstract

Recent advances in design and fabrication have increased the energy-relaxation times of isolated superconducting transmon qubits to the hundreds-of-microseconds regime, with reported values exceeding 500 $μ$s. However, the same progress has not automatically translated to multiqubit processors, where qubits are embedded in connected qubit-coupler lattices and often exhibit much shorter lifetimes than isolated qubits. To identify possible sources of this discrepancy, here we use finite-element simulation to investigate how surface participation ratios and the resulting surface dielectric loss change when a qubit is embedded in a flip-chip qubit-coupler lattice. Controlled comparisons show that higher connectivity can indeed lead to larger surface loss: in the simulated lattice, connecting a qubit to two and four couplers increases the surface loss by factors of 1.3 and 1.8, respectively. We attribute this change to the combined effects of added edge fields from coupling claws, field redistribution over the larger connected metal network, and hybridization with coupler modes. We further examine how this connectivity-induced surface-loss penalty depends on the geometric design parameters of both the qubit electrodes and the coupling claws, and derive guidelines for designing low-loss multiqubit processors.

The paper asks whether embedding transmons in connected qubit–coupler lattices increases surface dielectric loss relative to isolated-qubit designs. It uses finite-element eigenmode simulations of flip-chip geometries, with lumped-inductor Josephson junctions and a two-step participation-extraction method combining global 3D fields with local 2D edge corrections. Comparisons include an isolated qubit, passive coupling claws, and environments with one, two, or four active couplers. For the simulated qubit-like dressed modes, two and four couplers increase the estimated surface-loss rate by factors of $1.33$ and $1.80$, respectively; the one-coupler case remains near the isolated baseline. With the assumed interface loss tangents and a common frequency of $4.5\,\mathrm{GHz}$, these correspond to surface-loss-limited lifetimes of $99.5$ and $73.6\,\mu\mathrm{s}$ versus $132.7\,\mu\mathrm{s}$ in isolation. Four passive claws alone produce a $2.11$-fold penalty. Geometry and mode controls attribute the changes to added edge fields, field redistribution, and coupler-mode hybridization. Parameter sweeps show that larger qubit–ground gaps and opposite-chip holes can improve isolated-qubit lifetime while increasing the relative connectivity penalty. Coupling-claw modifications also change qubit-mode loss; an interdigitated claw–coupler capacitor yields a four-coupler penalty of $2.14$. The lifetimes are comparative estimates, not fabricated-device predictions: interface properties are assumed and process-dependent. Metal–air participation has additional edge-correction uncertainty. The simulations mainly characterize near-idle coupler biases rather than gate trajectories, and do not include other possible processor-loss channels such as Purcell decay, packaging modes, or seam loss.