Characterization and reduction of capacitive loss induced by sub-micron Josephson junction fabrication in superconducting qubits
A. Dunsworth, A. Megrant, Chris Quintana, Zijun Chen, R. Barends, Brian Burkett, Brooks Foxen, Yu Chen, B. Chiaro, Austin G. Fowler, R. Graff, Evan R. Jeffrey, J. Kelly, Erik A. Lucero, J. Mutus, M. Neeley, C. Neill, P. Roushan, D. Sank, A. Vainsencher, J. Wenner, T. White, John M. Martinis
Josephson junctions form the essential non-linearity for almost all superconducting qubits. The junction is formed when two superconducting electrodes come within ∼1 nm of each other. Although the capacitance of these electrodes is a small fraction of the total qubit capacitance, the nearby electric fields are more concentrated in dielectric surfaces and can contribute substantially to the total dissipation. We have developed a technique to experimentally investigate the effect of these electrodes on the quality of superconducting devices. We use λ/4 coplanar waveguide resonators to emulate lumped qubit capacitors. We add a variable number of these electrodes to the capacitive end of these resonators and measure how the additional loss scales with the number of electrodes. We then reduce this loss with fabrication techniques that limit the amount of lossy dielectrics. We then use these techniques for the fabrication of Xmon qubits on a silicon substrate to improve their energy relaxation times by a factor of 5.
Josephson junctions form the essential non-linearity for almost all superconducting qubits. The junction is formed when two superconducting electrodes come within ∼1 nm of each other. Although the capacitance of these electrodes is a small fraction of the total qubit capacitance, the nearby electric fields are more concentrated in dielectric surfaces and can contribute substantially to the total dissipation. We have developed a technique to experimentally investigate the effect of these electrodes on the quality of superconducting devices. We use λ/4 coplanar waveguide resonators to emulate lumped qubit capacitors. We add a variable number of these electrodes to the capacitive end of these resonators and measure how the additional loss scales with the number of electrodes. We then reduce this loss with fabrication techniques that limit the amount of lossy dielectrics. We then use these techniques for the fabrication of Xmon qubits on a silicon substrate to improve their energy relaxation times by a factor of 5.
We have measured the excited state lifetimes in Josephson junction phase and transmon qubits, all of which were fabricated with the same scalable multi-layer process. We have compared the lifetimes of phase qubits before and after removal of the isolating dielectric, SiN x , and find a fourfold improvement of the relaxation time after the removal. Together with the results from the transmon qubit and measurements on coplanar waveguide resonators, these measurements indicate that the lifetimes are limited by losses from the dielectric constituents of the qubits. We have extracted the individual loss contributions from the dielectrics in the tunnel junction barrier, AlO x , the isolating dielectric, SiN x , and the substrate, Si/SiO 2 , by weighting the total loss with the parts of the electric field over the different dielectric materials. Our results agree well with and complement the findings from other studies, demonstrating that superconducting qubits can be used as a reliable tool for high-frequency characterization of dielectric materials. We conclude with a discussion of how changes in design and material choice could improve qubit lifetimes by up to a factor of 4.
Quantum sensing and computation can be realized with superconducting microwave circuits. Qubits are engineered quantum systems of capacitors and inductors with non-linear Josephson junctions. They operate in the single-excitation quantum regime, photons of 27μeV at 6.5 GHz. Quantum coherence is fundamentally limited by materials defects, in particular atomic-scale parasitic two-level systems (TLS) in amorphous dielectrics at circuit interfaces.[1] The electric fields driving oscillating charges in quantum circuits resonantly couple to TLS, producing phase noise and dissipation. We use coplanar niobium-on-silicon superconducting resonators to probe decoherence in quantum circuits. By selectively modifying interface dielectrics, we show that most TLS losses come from the silicon surface oxide, and most non-TLS losses are distributed throughout the niobium surface oxide. Through post-fabrication interface modification we reduced TLS losses by 85% and non-TLS losses by 72%, obtaining record single-photon resonator quality factors above 5 million and approaching a regime where non-TLS losses are dominant. [1]Müller, C., Cole, J. H. & Lisenfeld, J. Towards understanding two-level-systems in amorphous solids: insights from quantum circuits. Rep. Prog. Phys. 82, 124501 (2019)
Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originate from Josephson junctions wiring and can limit qubit relaxation time. We experimentally extracted dielectric loss tangents of qubit elements and showed that dominant surface loss of wiring can occur for real qubits designs. Finally, we experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.
Fluxonium superconducting qubits have demonstrated long coherence times and high single- and two-qubit gate fidelities, making them a favorable building block for superconducting quantum processors. We investigate the dominant limitations to fluxonium qubit energy relaxation time T1 using a set of eight planar, aluminum-on-silicon qubits. We find that a circuit-based model for capacitive dielectric loss best captures the frequency dependence of T1, which we analyze within both a two-level and a six-level energy relaxation model. We convert the measured T1 into an effective capacitive quality factor QCeff to compare qubits on equal footing, accounting for independently estimated contributions from 1/f flux noise and radiative loss to the control and readout circuitry. We apply this methodology to compare qubits from two fabrication processes: a baseline process and one that applies a fluorine-based wet treatment prior to Josephson junction deposition. We resolve a small improvement of (13.8 ± 8.4)% in the process mean QCeff, indicating that the fluorine treatment may have reduced loss from the metal-substrate interface, but did not address the primary source of loss in these fluxonium qubits.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
The large physical size of superconducting qubits and their associated on-chip control structures presents a practical challenge toward building a large-scale quantum computer. In particular, transmons require a high-quality-factor shunting capacitance that is typically achieved by using a large coplanar capacitor. Other components, such as superconducting microwave resonators used for qubit state readout, are typically constructed from coplanar waveguides, which are millimeters in length. Here, we use compact superconducting through-silicon vias to realize lumped-element capacitors in both qubits and readout resonators to significantly reduce the on-chip footprint of both of these circuit elements. We measure two types of devices to show that through-silicon vias are of sufficient quality to be used as capacitive circuit elements and provide a significant reduction in size over existing approaches.