[Background] The industrial usefulness of a quantum processor is correlated with its scalability; thus, one of the main focuses of current industrial and academic efforts is to upscale this machine. For trapped-ion quantum processors, some of the most promising scalable architectures require ion transport across surface-segmented traps. Published solutions for the control of ion transport have been mostly developed as bulky, rack-based embedded systems, placed at room temperature outside the vacuum/cryostat chambers, with cables fed in, and with voltages time-multiplexed or broadcast to reach the electrodes of the trap in order to apply the fixed pre-computed raw voltage sets for each fabricated ion trap, where the voltages are tailored to its time- and setup-dependent deposited impurities condition; all of which is neither scalable nor optimally efficient. [Objective] To address this gap, this study proposes a DiQuNET scalable integrated microelectronics solution for ion-transport control. [Methods]We describe the system-level integration strategy and a full engineering development cycle of the device. [Results] This work presents the conception (specification and design) of the ion-transport integrated circuit and the realization (implementation and evaluation) of a proof of concept (TRL 3), which also constitutes a proof of principle of the first DiQuNET compliant integrated circuit. [Conclusion] These results verify and validate the design of an efficient, architecture-scalable, trainable, automated, parametric, and re-configurable proof of concept of the ion-transport integrated circuit. These results support the feasibility, efficiency, and viability potential of the DiQuNET paradigm that uses a distributed set ofautomatamachines to control a quantum processor.
[Background] The industrial usefulness of a quantum processor is correlated with its scalability; thus, one of the main focuses of current industrial and academic efforts is to upscale this machine. For trapped-ion quantum processors, some of the most promising scalable architectures require ion transport across surface-segmented traps. Published solutions for the control of ion transport have been mostly developed as bulky, rack-based embedded systems, placed at room temperature outside the vacuum/cryostat chambers, with cables fed in, and with voltages time-multiplexed or broadcast to reach the electrodes of the trap in order to apply the fixed pre-computed raw voltage sets for each fabricated ion trap, where the voltages are tailored to its time- and setup-dependent deposited impurities condition; all of which is neither scalable nor optimally efficient. [Objective] To address this gap, this study proposes a DiQuNET scalable integrated microelectronics solution for ion-transport control. [Methods]We describe the system-level integration strategy and a full engineering development cycle of the device. [Results] This work presents the conception (specification and design) of the ion-transport integrated circuit and the realization (implementation and evaluation) of a proof of concept (TRL 3), which also constitutes a proof of principle of the first DiQuNET compliant integrated circuit. [Conclusion] These results verify and validate the design of an efficient, architecture-scalable, trainable, automated, parametric, and re-configurable proof of concept of the ion-transport integrated circuit. These results support the feasibility, efficiency, and viability potential of the DiQuNET paradigm that uses a distributed set ofautomatamachines to control a quantum processor.
[Background] Scalability is the only DiVincenzo criterion that has not yet been achieved at utility-scale and fault-tolerant levels by any quantum processor. These quantum machines are governed by a classical control system that must scale along with the quantum objects it controls. For the case study of trapped-ion quantum processors, mostly massive room-temperature, rack-based, and non-integrated solutions for its control system are described in literature, which is neither scalable nor efficient. Thus, the control system poses an engineering bottleneck for the scalability of quantum processors. [Objective] Therefore, this study aims to address this gap by proposing a scalable microelectronics-based control architecture blueprint. [Methods] Our method relies on an electronic system-level top-down design methodology, and we illustrate the concepts through a case study. [Results] In this study, we first challenge thestatus quofor the use case of a quantum processor and propose a more pragmatic approach. Second, we present the DiQuNET architecture, which is a system-level architecture for the control of a quantum processor. Finally, we present a case study in which we map the architecture to control a specific quantum processor technology, subsystem, and functionality. [Conclusion] Our proposal is an innately scalable and controldistributed system architecture whose features aim to support the execution of a quantum algorithm at utility-scale levels and embed hardware to support fault-tolerance. It raises the hardware interface of the processor to an algorithm level and opens the door to the joint community and industrial realization of the control system for quantum processors.
[Background] Quantum processors offer a new paradigm for computing which can more accurately model –simulate– the intrinsic quantum nature of microscopic phenomena, can more efficiently compute algorithms with a quantum formulation versus that of their classical formulation, and has been shown to have a higher energy efficiency than classical processors when solving the same problem. Yet, the practical physical implementation of quantum processors is inherently transient, stochastic, and prone to perturbations, which makes the best-performing quantum processor to date to sink in errors before it can get past the 25th circuit gate layer of computation with its 25 quantum bits. A quantum processor promises us benefits, but only if built within a utility-scale size, currently estimated to be of about O(10^6) quantum bits x O(10^9) gate layers, and if we manage to overcome its errors by engineering it fault-tolerantly. After about 30 years in the pursuit of building this machine, we are several orders of magnitude away from usefulness. The challenge is such that this machine potentially boils down to be the largest-scale and most-challenging engineering project that human kind pursues to build during the 21st century. Accordingly, this challenge must be approached with a pragmatic engineering mindset. [Objective] Therefore, this work takes an engineering approach to define a system-level control paradigm for quantum processors, which enables scalability, reliability, usefulness, efficiency, sustainability, and resilience, within the case study of trapped ions. [Methods] In this work, I apply engineering methods, namely, systems and control engineering for the development of a machine. The first step is to clearly understand and describe the problem and what is at stake along the expectations of a current worldwide quantum investment in the US$ O(10^9). To that end, I examine existing prior art through a systematic literature review and conduct numerous interviews of European physicists in order to comprehend the status quo of quantum computing. Second, I use a top-down system-level methodology for the conception of the control system of quantum processors. Finally, I realize a proof of concept for one constituent machine compliant to the system-level proposal. [Results] In light of examining the status quo strategy for quantum computing, I must challenge it and advocate to redirect our efforts towards building this machine as a closed-loop locked-algorithm control system in order to ultimately enable its resilience. First, I propose the top-level ASQP machine and the DiQuNET architecture as novel paradigm for the control of quantum processors. Second, I develop a proof of concept of the first DiQuIC: the ITIC, which is a constituent machine of the DiQuNET system that implements a particular functional task in a trapped-ion quantum processor. [Conclusion] The ASQP is a novel system-level use-case proposal for a quantum processor. The DiQuNET paradigm is a novel system-level proposal for the physical control implementation of the quantum Turing machine. Overall, the control paradigm endows a quantum processor with scalability, reliability, usefulness, sustainability, efficiency, and resilience features. It is a proposal that opens the door to the standardization, the industrial realization, and the human-resources distributed and collaborative development of the control system of quantum processors. Cite this thesis as: S. Castillo, “The DiQuNET Paradigm for the Control of Quantum Processors: The case for Trapped Ions,” Doctoral Thesis, University of Innsbruck, Dept. Mechatron., Innsbruck, Austria, 2026. doi: https://doi.org/10.5281/zenodo.23236620 Thesis information: Grade: 1 (excellent)ISCED-11 Level 8 * Advisors: Prof. T. Northup (UIBK, AT) and Prof. E. Charbon (EPFL, CH)* Evaluator: Prof. R. van Meter (Keio Uni, JP & Editor-in-Chief of IEEE TQE)* Tech-transfer Mentor: Jamie Urquhart (Founder of ARM. Ltd., UK) Revision history: 2026-03-27: First release v1.02026-09-29: Release v2.0: updated intro, chap. 1, and biography.
[Background] Ions in an ion trap are among the most promising technologies to implement a quantum processor. This machine is governed by a classic electronic control system, for which we found no systematic electronic system-level approach for its conception, design, implementation, and/or verification. The trapped-ion quantum processor cannot advance its roadmap without an appropriate and fitting electronic control system. To fully enable further advancements in the field, an understanding of the electronic control system as a system of its own and the conception of its electronic system-level description, are due needed. [Objective] Therefore, we want to address the electronic control system of a trapped-ion quantum processor as a system of its own by first identifying its published literature. [Method] For that purpose, we conducted a systematic literature review abiding by the APISSER methodology for systematic literature reviews in engineering, which describes and delimits the reach of this study. [Results] In this paper, we report the results of the study, classify them, and present possible research directions and considerations to be taken in the conception of this system. [Conclusion] This study lays a introductory foundation to grasp the requirements and environment of the electronic control system of a trapped-ion quantum processor. A foundation much needed to leverage further research on this topic by the engineering community. Furthermore, it serves as a checkpoint in time: listing and synthesizing, the existing published body-of-knowledge of this topic within the defined boundaries of our method.
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
Trapped-ion quantum computers based on the quantum charge-coupled device architecture require on the order of ten trap electrodes per qubit, making the number of vacuum feedthroughs a bottleneck at the system scale. Time-division multiplexed (TDM)-based voltage control for trap electrodes provides a natural route to alleviate this constraint. However, previous studies have been limited to architectural proposals for static trap-potential compensation and room-temperature demonstrations of dynamic-electrode control, leaving cryogenic operation of TDM-based voltage control for static and dynamic electrodes experimentally unexplored. In this study, we develop and cryogenically validate TDM-based voltage control schemes for two distinct electrode classes. For static electrodes used in trap-potential compensation, we implement a 32-channel demultiplexed system operating at approximately 27~K, achieving an effective voltage update rate of 37.5~kHz with an output range of ±10V per channel. For dynamic electrodes used in ion operations, such as shuttling, we implement a four-channel demultiplexed system operating at approximately 14~K, achieving an effective voltage update rate of 1~MHz with a comparable output range. These results establish TDM-based voltage control as a practical approach for both electrode classes, providing a path for mitigating the vacuum feedthrough bottleneck in scalable trapped-ion quantum processors.
The scaling up of trapped-ion quantum processors based on the quantum charge-coupled device (QCCD) architecture is difficult owing to the extensive electronics and high-density wiring required to control numerous trap electrodes. In conventional QCCD architectures, each trap electrode is controlled via a dedicated digital-to-analog converter (DAC). The conventional approach places an overwhelming demand on electronic resources and wiring complexity. This is because the number of trap electrodes typically exceeds the number of trapped-ion qubits. This study proposes a method that leverages a high-speed DAC to generate time-division multiplexed signals to control a large-scale QCCD trapped-ion quantum processor. The proposed method replaces conventional DACs with a single high-speed DAC that generates the complete voltage waveforms required to control the trap electrodes, thereby significantly reducing the wiring complexity and overall resource requirements. Based on realistic parameters and commercially available electronics, our analysis demonstrates that a QCCD trapped-ion quantum computer with10,000trap electrodes can be controlled using only 13 field-programmable gate arrays and 104 high-speed DACs. This is in stark contrast to the10,000dedicated DACs required by conventional control methods. Consequently, employing this approach, we developed a proof-of-concept electronic system and evaluated its analog output performance.