[Background] Scalability is the only DiVincenzo criterion that has not yet been achieved at utility-scale and fault-tolerant levels by any quantum processor. These quantum machines are governed by a classical control system that must scale along with the quantum objects it controls. For the case study of trapped-ion quantum processors, mostly massive room-temperature, rack-based, and non-integrated solutions for its control system are described in literature, which is neither scalable nor efficient. Thus, the control system poses an engineering bottleneck for the scalability of quantum processors. [Objective] Therefore, this study aims to address this gap by proposing a scalable microelectronics-based control architecture blueprint. [Methods] Our method relies on an electronic system-level top-down design methodology, and we illustrate the concepts through a case study. [Results] In this study, we first challenge thestatus quofor the use case of a quantum processor and propose a more pragmatic approach. Second, we present the DiQuNET architecture, which is a system-level architecture for the control of a quantum processor. Finally, we present a case study in which we map the architecture to control a specific quantum processor technology, subsystem, and functionality. [Conclusion] Our proposal is an innately scalable and controldistributed system architecture whose features aim to support the execution of a quantum algorithm at utility-scale levels and embed hardware to support fault-tolerance. It raises the hardware interface of the processor to an algorithm level and opens the door to the joint community and industrial realization of the control system for quantum processors.
[Background] Scalability is the only DiVincenzo criterion that has not yet been achieved at utility-scale and fault-tolerant levels by any quantum processor. These quantum machines are governed by a classical control system that must scale along with the quantum objects it controls. For the case study of trapped-ion quantum processors, mostly massive room-temperature, rack-based, and non-integrated solutions for its control system are described in literature, which is neither scalable nor efficient. Thus, the control system poses an engineering bottleneck for the scalability of quantum processors. [Objective] Therefore, this study aims to address this gap by proposing a scalable microelectronics-based control architecture blueprint. [Methods] Our method relies on an electronic system-level top-down design methodology, and we illustrate the concepts through a case study. [Results] In this study, we first challenge thestatus quofor the use case of a quantum processor and propose a more pragmatic approach. Second, we present the DiQuNET architecture, which is a system-level architecture for the control of a quantum processor. Finally, we present a case study in which we map the architecture to control a specific quantum processor technology, subsystem, and functionality. [Conclusion] Our proposal is an innately scalable and controldistributed system architecture whose features aim to support the execution of a quantum algorithm at utility-scale levels and embed hardware to support fault-tolerance. It raises the hardware interface of the processor to an algorithm level and opens the door to the joint community and industrial realization of the control system for quantum processors.
[Background] Quantum processors offer a new paradigm for computing which can more accurately model –simulate– the intrinsic quantum nature of microscopic phenomena, can more efficiently compute algorithms with a quantum formulation versus that of their classical formulation, and has been shown to have a higher energy efficiency than classical processors when solving the same problem. Yet, the practical physical implementation of quantum processors is inherently transient, stochastic, and prone to perturbations, which makes the best-performing quantum processor to date to sink in errors before it can get past the 25th circuit gate layer of computation with its 25 quantum bits. A quantum processor promises us benefits, but only if built within a utility-scale size, currently estimated to be of about O(10^6) quantum bits x O(10^9) gate layers, and if we manage to overcome its errors by engineering it fault-tolerantly. After about 30 years in the pursuit of building this machine, we are several orders of magnitude away from usefulness. The challenge is such that this machine potentially boils down to be the largest-scale and most-challenging engineering project that human kind pursues to build during the 21st century. Accordingly, this challenge must be approached with a pragmatic engineering mindset. [Objective] Therefore, this work takes an engineering approach to define a system-level control paradigm for quantum processors, which enables scalability, reliability, usefulness, efficiency, sustainability, and resilience, within the case study of trapped ions. [Methods] In this work, I apply engineering methods, namely, systems and control engineering for the development of a machine. The first step is to clearly understand and describe the problem and what is at stake along the expectations of a current worldwide quantum investment in the US$ O(10^9). To that end, I examine existing prior art through a systematic literature review and conduct numerous interviews of European physicists in order to comprehend the status quo of quantum computing. Second, I use a top-down system-level methodology for the conception of the control system of quantum processors. Finally, I realize a proof of concept for one constituent machine compliant to the system-level proposal. [Results] In light of examining the status quo strategy for quantum computing, I must challenge it and advocate to redirect our efforts towards building this machine as a closed-loop locked-algorithm control system in order to ultimately enable its resilience. First, I propose the top-level ASQP machine and the DiQuNET architecture as novel paradigm for the control of quantum processors. Second, I develop a proof of concept of the first DiQuIC: the ITIC, which is a constituent machine of the DiQuNET system that implements a particular functional task in a trapped-ion quantum processor. [Conclusion] The ASQP is a novel system-level use-case proposal for a quantum processor. The DiQuNET paradigm is a novel system-level proposal for the physical control implementation of the quantum Turing machine. Overall, the control paradigm endows a quantum processor with scalability, reliability, usefulness, sustainability, efficiency, and resilience features. It is a proposal that opens the door to the standardization, the industrial realization, and the human-resources distributed and collaborative development of the control system of quantum processors. Cite this thesis as: S. Castillo, “The DiQuNET Paradigm for the Control of Quantum Processors: The case for Trapped Ions,” Doctoral Thesis, University of Innsbruck, Dept. Mechatron., Innsbruck, Austria, 2026. doi: https://doi.org/10.5281/zenodo.23236620 Thesis information: Grade: 1 (excellent)ISCED-11 Level 8 * Advisors: Prof. T. Northup (UIBK, AT) and Prof. E. Charbon (EPFL, CH)* Evaluator: Prof. R. van Meter (Keio Uni, JP & Editor-in-Chief of IEEE TQE)* Tech-transfer Mentor: Jamie Urquhart (Founder of ARM. Ltd., UK) Revision history: 2026-03-27: First release v1.02026-09-29: Release v2.0: updated intro, chap. 1, and biography.
[Background] The industrial usefulness of a quantum processor is correlated with its scalability; thus, one of the main focuses of current industrial and academic efforts is to upscale this machine. For trapped-ion quantum processors, some of the most promising scalable architectures require ion transport across surface-segmented traps. Published solutions for the control of ion transport have been mostly developed as bulky, rack-based embedded systems, placed at room temperature outside the vacuum/cryostat chambers, with cables fed in, and with voltages time-multiplexed or broadcast to reach the electrodes of the trap in order to apply the fixed pre-computed raw voltage sets for each fabricated ion trap, where the voltages are tailored to its time- and setup-dependent deposited impurities condition; all of which is neither scalable nor optimally efficient. [Objective] To address this gap, this study proposes a DiQuNET scalable integrated microelectronics solution for ion-transport control. [Methods]We describe the system-level integration strategy and a full engineering development cycle of the device. [Results] This work presents the conception (specification and design) of the ion-transport integrated circuit and the realization (implementation and evaluation) of a proof of concept (TRL 3), which also constitutes a proof of principle of the first DiQuNET compliant integrated circuit. [Conclusion] These results verify and validate the design of an efficient, architecture-scalable, trainable, automated, parametric, and re-configurable proof of concept of the ion-transport integrated circuit. These results support the feasibility, efficiency, and viability potential of the DiQuNET paradigm that uses a distributed set ofautomatamachines to control a quantum processor.
[Background] Ions in an ion trap are among the most promising technologies to implement a quantum processor. This machine is governed by a classic electronic control system, for which we found no systematic electronic system-level approach for its conception, design, implementation, and/or verification. The trapped-ion quantum processor cannot advance its roadmap without an appropriate and fitting electronic control system. To fully enable further advancements in the field, an understanding of the electronic control system as a system of its own and the conception of its electronic system-level description, are due needed. [Objective] Therefore, we want to address the electronic control system of a trapped-ion quantum processor as a system of its own by first identifying its published literature. [Method] For that purpose, we conducted a systematic literature review abiding by the APISSER methodology for systematic literature reviews in engineering, which describes and delimits the reach of this study. [Results] In this paper, we report the results of the study, classify them, and present possible research directions and considerations to be taken in the conception of this system. [Conclusion] This study lays a introductory foundation to grasp the requirements and environment of the electronic control system of a trapped-ion quantum processor. A foundation much needed to leverage further research on this topic by the engineering community. Furthermore, it serves as a checkpoint in time: listing and synthesizing, the existing published body-of-knowledge of this topic within the defined boundaries of our method.
Scaling bottlenecks the making of digital quantum computers, posing challenges from both the quantum and the classical components. We present a classical architecture to cope with a comprehensive list of the latter challenges all at once , and implement it fully in an end-to-end system by integrating a multi-core RISC-V CPU with our in-house control electronics. Our architecture enables scalable, high-precision control of large quantum processors and accommodates evolving requirements of quantum hardware. A central feature is a microarchitecture executing quantum operations in parallel on arbitrary predefined qubit groups. Another key feature is a reconfigurable quantum instruction set that supports easy qubit re-grouping and instructions extensions. As a demonstration, we implement the widely-studied surface code quantum computing workflow, which is instructive for being demanding on both the controllers and the integrated classical computation. Our design, for the first time, reduces instruction issuing and transmission costs to constants, which do not scale with the number of qubits, without adding any overheads in decoding or dispatching. Our system uses a dedicated general-purpose CPU for both qubit control and classical computation, including syndrome decoding. Implementing recent theoretical proposals as decoding firmware that parallelizes general inner decoders, we can achieve unprecedented decoding capabilities of up to distances 47 and 67 with the currently available systems-on-chips for physical error rate p = 0.001 and p = 0.0001, respectively, all in just 1 μs.
Abstract The immense resource overhead of full quantum error correction (QEC) presents a formidable barrier to achiev- ing fault-tolerant quantum computation. This paper introduces a hybrid analog-digital quantum processor architecture designed as a pragmatic strategy for achieving ”mid-scale fault tolerance” (MSFT). We formally define MSFT as a hardware-level error suppression scheme that achieves a fidelity gain by replacing deep, error-prone digital gate sequences with single, high-fidelity analog evolution blocks. The architecture comprises a programmable digital core for state preparation and measurement, coupled to an analog co-processor that executes computationally intensive Hamiltonian evolutions. This approach reduces the effective logical depth and error accumulation for algorithms like VQE. We validate this claim with statistically robust simulations on standard molecular Hamiltonians (LiH and BeH), demonstrating a significant performance advantage over purely digital systems based on an aggregation of 50 independent simulation trials. The analysis includes scalability and a discussion of the critical digital-analog interface, proposing trapped-ion and neutral-atom systems as viable physical platforms
Quantum computing has made significant strides, with hardware platforms now advanced enough to tackle the challenges of scaling up to larger and more robust systems. Central to this progression is the interface between quantum processors, comprising isolated qubits, and the classical systems required for their control and readout. As these systems transition from few-qubit devices to fault-tolerant architectures, the complexity of this quantum-classical interaction poses significant engineering challenges. Field-Programmable Gate Arrays (FPGAs) have emerged as an adaptable and efficient solution, offering realtime control, low-latency operations, and seamless integration. This review delves into current FPGA-based platforms, including commercial systems, as well as open-source solutions developed by academic research groups. The architecture, features, and contributions of these platforms to addressing scalability and integration issues are thoroughly examined. Additionally, the review highlights innovations in cryogeniccompatible controllers and explores the potential of Cryo-FPGAs to reduce noise and improve fidelity in quantum systems. By providing a comprehensive analysis of current technologies and identifying opportunities for advancement, this review offers valuable insights for researchers and engineers working to develop scalable quantum computing solutions.