Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

The DiQuNET Paradigm for the Control of Quantum Processors: The case for Trapped Ions

Stefanie Castillo

Published Sep 29, 2026• 0 citations
Publisher

Abstract

[Background] Quantum processors offer a new paradigm for computing which can more accurately model –simulate– the intrinsic quantum nature of microscopic phenomena, can more efficiently compute algorithms with a quantum formulation versus that of their classical formulation, and has been shown to have a higher energy efficiency than classical processors when solving the same problem. Yet, the practical physical implementation of quantum processors is inherently transient, stochastic, and prone to perturbations, which makes the best-performing quantum processor to date to sink in errors before it can get past the 25th circuit gate layer of computation with its 25 quantum bits. A quantum processor promises us benefits, but only if built within a utility-scale size, currently estimated to be of about O(10^6) quantum bits x O(10^9) gate layers, and if we manage to overcome its errors by engineering it fault-tolerantly. After about 30 years in the pursuit of building this machine, we are several orders of magnitude away from usefulness. The challenge is such that this machine potentially boils down to be the largest-scale and most-challenging engineering project that human kind pursues to build during the 21st century. Accordingly, this challenge must be approached with a pragmatic engineering mindset. [Objective] Therefore, this work takes an engineering approach to define a system-level control paradigm for quantum processors, which enables scalability, reliability, usefulness, efficiency, sustainability, and resilience, within the case study of trapped ions. [Methods] In this work, I apply engineering methods, namely, systems and control engineering for the development of a machine. The first step is to clearly understand and describe the problem and what is at stake along the expectations of a current worldwide quantum investment in the US$ O(10^9). To that end, I examine existing prior art through a systematic literature review and conduct numerous interviews of European physicists in order to comprehend the status quo of quantum computing. Second, I use a top-down system-level methodology for the conception of the control system of quantum processors. Finally, I realize a proof of concept for one constituent machine compliant to the system-level proposal. [Results] In light of examining the status quo strategy for quantum computing, I must challenge it and advocate to redirect our efforts towards building this machine as a closed-loop locked-algorithm control system in order to ultimately enable its resilience. First, I propose the top-level ASQP machine and the DiQuNET architecture as novel paradigm for the control of quantum processors. Second, I develop a proof of concept of the first DiQuIC: the ITIC, which is a constituent machine of the DiQuNET system that implements a particular functional task in a trapped-ion quantum processor. [Conclusion] The ASQP is a novel system-level use-case proposal for a quantum processor. The DiQuNET paradigm is a novel system-level proposal for the physical control implementation of the quantum Turing machine. Overall, the control paradigm endows a quantum processor with scalability, reliability, usefulness, sustainability, efficiency, and resilience features. It is a proposal that opens the door to the standardization, the industrial realization, and the human-resources distributed and collaborative development of the control system of quantum processors. Cite this thesis as: S. Castillo, “The DiQuNET Paradigm for the Control of Quantum Processors: The case for Trapped Ions,” Doctoral Thesis, University of Innsbruck, Dept. Mechatron., Innsbruck, Austria, 2026. doi: https://doi.org/10.5281/zenodo.23236620 Thesis information: Grade: 1 (excellent)ISCED-11 Level 8 * Advisors: Prof. T. Northup (UIBK, AT) and Prof. E. Charbon (EPFL, CH)* Evaluator: Prof. R. van Meter (Keio Uni, JP & Editor-in-Chief of IEEE TQE)* Tech-transfer Mentor: Jamie Urquhart (Founder of ARM. Ltd., UK) Revision history: 2026-03-27: First release v1.02026-09-29: Release v2.0: updated intro, chap. 1, and biography.

DOI
10.5281/zenodo.23236619

Related papers

The DiQuNET Architecture for the Control of Quantum Processors: The Case Study of Trapped Ions

Stefanie Castillo

[Background] Scalability is the only DiVincenzo criterion that has not yet been achieved at utility-scale and fault-tolerant levels by any quantum processor. These quantum machines are governed by a classical control system that must scale along with the quantum objects it controls. For the case study of trapped-ion quantum processors, mostly massive room-temperature, rack-based, and non-integrated solutions for its control system are described in literature, which is neither scalable nor efficient. Thus, the control system poses an engineering bottleneck for the scalability of quantum processors. [Objective] Therefore, this study aims to address this gap by proposing a scalable microelectronics-based control architecture blueprint. [Methods] Our method relies on an electronic system-level top-down design methodology, and we illustrate the concepts through a case study. [Results] In this study, we first challenge thestatus quofor the use case of a quantum processor and propose a more pragmatic approach. Second, we present the DiQuNET architecture, which is a system-level architecture for the control of a quantum processor. Finally, we present a case study in which we map the architecture to control a specific quantum processor technology, subsystem, and functionality. [Conclusion] Our proposal is an innately scalable and controldistributed system architecture whose features aim to support the execution of a quantum algorithm at utility-scale levels and embed hardware to support fault-tolerance. It raises the hardware interface of the processor to an algorithm level and opens the door to the joint community and industrial realization of the control system for quantum processors.

IEEE Access•Jan 1, 2026•1 citation

The DiQuNET Ion-Transport IC of a Trapped-Ion Quantum Processor: A PoC

Stefanie Castillo

[Background] The industrial usefulness of a quantum processor is correlated with its scalability; thus, one of the main focuses of current industrial and academic efforts is to upscale this machine. For trapped-ion quantum processors, some of the most promising scalable architectures require ion transport across surface-segmented traps. Published solutions for the control of ion transport have been mostly developed as bulky, rack-based embedded systems, placed at room temperature outside the vacuum/cryostat chambers, with cables fed in, and with voltages time-multiplexed or broadcast to reach the electrodes of the trap in order to apply the fixed pre-computed raw voltage sets for each fabricated ion trap, where the voltages are tailored to its time- and setup-dependent deposited impurities condition; all of which is neither scalable nor optimally efficient. [Objective] To address this gap, this study proposes a DiQuNET scalable integrated microelectronics solution for ion-transport control. [Methods]We describe the system-level integration strategy and a full engineering development cycle of the device. [Results] This work presents the conception (specification and design) of the ion-transport integrated circuit and the realization (implementation and evaluation) of a proof of concept (TRL 3), which also constitutes a proof of principle of the first DiQuNET compliant integrated circuit. [Conclusion] These results verify and validate the design of an efficient, architecture-scalable, trainable, automated, parametric, and re-configurable proof of concept of the ion-transport integrated circuit. These results support the feasibility, efficiency, and viability potential of the DiQuNET paradigm that uses a distributed set ofautomatamachines to control a quantum processor.

IEEE Access•Jan 1, 2026•1 citation

Comprehensive Review of Quantum Computing Technologies and Processor Architectures

Babu shanmugham

This paper presents a comprehensive review of quantum computing and the technological foundations of quantum processors. Quantum computing represents a transformative computational paradigm that leverages the fundamental principles of quantum mechanics—such as superposition, entanglement, and quantum interference—to solve complex problems that are intractable for classical computers. At the core of this paradigm lies the quantum processor, a specialized hardware system designed to initialize, control, and measure quantum bits (qubits) through precise gate operations and coherent interactions. The survey examines the essential theoretical concepts underlying quantum computation and provides a structured comparison of leading quantum processor platforms. Prominent architectures, including superconducting circuits, trapped-ion systems, and photonic implementations, are analyzed in terms of their physical mechanisms, scalability, coherence properties, and engineering challenges. Each platform offers distinct advantages and faces specific technical limitations related to noise, error correction, and fabrication complexity. In addition to reviewing hardware developments, this study highlights key obstacles in advancing quantum processors toward large-scale, fault-tolerant systems. Issues such as qubit stability, error mitigation, thermal management, and system integration are discussed to present a realistic perspective on current progress. Performance indicators including gate fidelity, coherence time, connectivity, and scalability are used to compare architectural approaches. The objective of this paper is to provide a clear and organized synthesis of recent advancements in quantum computing hardware, thereby offering researchers and practitioners a foundational reference to support continued innovation and development in this rapidly evolving field.

International Journal of Engineering Development and Research•Mar 1, 2026•0 citations

The Electronic Control System of a Trapped-Ion Quantum Processor: A Systematic Literature Review

Stefanie Castillo

[Background] Ions in an ion trap are among the most promising technologies to implement a quantum processor. This machine is governed by a classic electronic control system, for which we found no systematic electronic system-level approach for its conception, design, implementation, and/or verification. The trapped-ion quantum processor cannot advance its roadmap without an appropriate and fitting electronic control system. To fully enable further advancements in the field, an understanding of the electronic control system as a system of its own and the conception of its electronic system-level description, are due needed. [Objective] Therefore, we want to address the electronic control system of a trapped-ion quantum processor as a system of its own by first identifying its published literature. [Method] For that purpose, we conducted a systematic literature review abiding by the APISSER methodology for systematic literature reviews in engineering, which describes and delimits the reach of this study. [Results] In this paper, we report the results of the study, classify them, and present possible research directions and considerations to be taken in the conception of this system. [Conclusion] This study lays a introductory foundation to grasp the requirements and environment of the electronic control system of a trapped-ion quantum processor. A foundation much needed to leverage further research on this topic by the engineering community. Furthermore, it serves as a checkpoint in time: listing and synthesizing, the existing published body-of-knowledge of this topic within the defined boundaries of our method.

IEEE Access•Jan 1, 2023•10 citations

QUANTUM ARCHITECTONICS: THE PASSIVE PATH TO SCALE

Rowan Brad Quni-Gudzinas

The current approach to building quantum computers relies on a strategy of brute force intervention. Engineers attempt to force fragile quantum states to survive by constantly correcting their errors with external machinery. This method treats the quantum bit, or qubit, as an inherently unstable object that must be propped up. It assumes that if we simply build faster control loops, we can outrun the natural decay of the system. However, this perspective ignores the fundamental cost of fighting nature. Every time we correct an error, we are fighting against the natural tendency of the universe to increase disorder. This fight requires energy, and that energy must go somewhere. The reliance on active error correction creates a vicious cycle of energy consumption. As we add more qubits to the system, the number of errors increases. To fix these errors, we need more control hardware and more processing power. This additional hardware generates heat, which disturbs the sensitive quantum states even more. The more we try to fix the system, the more we disturb it. It is like trying to calm a pool of water by slapping the waves flat. The very act of intervention creates new ripples that require further correction. This scaling problem is not just a matter of engineering difficulty; it is a matter of physics. There is a limit to how fast and how efficiently we can extract entropy, or disorder, from a system. Current architectures are approaching this limit rapidly. We are building systems that require massive cooling infrastructure just to keep the control electronics from melting the qubits. This is not a sustainable path to a useful computer. We need a fundamentally different approach. The brute force method also introduces a complexity bottleneck. The software required to track and correct errors in real-time is becoming impossibly complex. We are trying to simulate a perfect machine using imperfect parts, and the overhead is crushing. The ratio of physical qubits needed to build one logical qubit is skyrocketing. We are spending all our resources on error correction, leaving little for actual computation. This is the definition of a diminishing return. We must recognize that the “active” paradigm is a trap. It lures us in with the promise of total control, but it hides the thermodynamic bill. That bill is coming due, and it is higher than we can pay. We cannot simply scale our way out of this problem with more power. We need to stop fighting the environment and start designing systems that are naturally stable. We need to move from active correction to passive protection.

•Feb 7, 2026•0 citations

Towards a scalable quantum computer

Carmen G. Almudéver, Nader Khammassi, Louis Hutin +5 more

A quantum machine may solve some complex problems that are intractable for even the most powerful classical computers. By exploiting quantum superposition and entanglement phenomena, quantum algorithms can achieve from polynomial to exponential speed up when compared to their best classical counterparts. A quantum computer will be a part of a heterogeneous, multi-core computer in which a classical processor will interact with several accelerators such as FPGAs, GPUs and also a quantum co-processor. Figure 1 shows the different layers of the quantum computer system stack [1]. Building such a quantum system requires contributions from different fields such as physics, electronics, computer science and computer engineering for addressing the following challenges: i) build scalable quantum chips integrating qubits with long coherence times and high-fidelity operations, ii) develop classical control electronics at possibly cryogenic temperatures and iii) create the microarchitecture as well as the software for quantum computation.

International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)•Apr 1, 2018•7 citations
[Background] Quantum processors offer a new paradigm for computing which can more accurately model –simulate– the intrinsic quantum nature of microscopic phenomena, can more efficiently compute algorithms with a quantum formulation versus that of their classical formulation, and has been shown to have a higher energy efficiency than classical processors when solving the same problem. Yet, the practical physical implementation of quantum processors is inherently transient, stochastic, and prone to perturbations, which makes the best-performing quantum processor to date to sink in errors before it can get past the 25th circuit gate layer of computation with its 25 quantum bits. A quantum processor promises us benefits, but only if built within a utility-scale size, currently estimated to be of about O(10^6) quantum bits x O(10^9) gate layers, and if we manage to overcome its errors by engineering it fault-tolerantly. After about 30 years in the pursuit of building this machine, we are several orders of magnitude away from usefulness. The challenge is such that this machine potentially boils down to be the largest-scale and most-challenging engineering project that human kind pursues to build during the 21st century. Accordingly, this challenge must be approached with a pragmatic engineering mindset. [Objective] Therefore, this work takes an engineering approach to define a system-level control paradigm for quantum processors, which enables scalability, reliability, usefulness, efficiency, sustainability, and resilience, within the case study of trapped ions. [Methods] In this work, I apply engineering methods, namely, systems and control engineering for the development of a machine. The first step is to clearly understand and describe the problem and what is at stake along the expectations of a current worldwide quantum investment in the US$ O(10^9). To that end, I examine existing prior art through a systematic literature review and conduct numerous interviews of European physicists in order to comprehend the status quo of quantum computing. Second, I use a top-down system-level methodology for the conception of the control system of quantum processors. Finally, I realize a proof of concept for one constituent machine compliant to the system-level proposal. [Results] In light of examining the status quo strategy for quantum computing, I must challenge it and advocate to redirect our efforts towards building this machine as a closed-loop locked-algorithm control system in order to ultimately enable its resilience. First, I propose the top-level ASQP machine and the DiQuNET architecture as novel paradigm for the control of quantum processors. Second, I develop a proof of concept of the first DiQuIC: the ITIC, which is a constituent machine of the DiQuNET system that implements a particular functional task in a trapped-ion quantum processor. [Conclusion] The ASQP is a novel system-level use-case proposal for a quantum processor. The DiQuNET paradigm is a novel system-level proposal for the physical control implementation of the quantum Turing machine. Overall, the control paradigm endows a quantum processor with scalability, reliability, usefulness, sustainability, efficiency, and resilience features. It is a proposal that opens the door to the standardization, the industrial realization, and the human-resources distributed and collaborative development of the control system of quantum processors. Cite this thesis as: S. Castillo, “The DiQuNET Paradigm for the Control of Quantum Processors: The case for Trapped Ions,” Doctoral Thesis, University of Innsbruck, Dept. Mechatron., Innsbruck, Austria, 2026. doi: https://doi.org/10.5281/zenodo.23236620 Thesis information: Grade: 1 (excellent)ISCED-11 Level 8 * Advisors: Prof. T. Northup (UIBK, AT) and Prof. E. Charbon (EPFL, CH)* Evaluator: Prof. R. van Meter (Keio Uni, JP & Editor-in-Chief of IEEE TQE)* Tech-transfer Mentor: Jamie Urquhart (Founder of ARM. Ltd., UK) Revision history: 2026-03-27: First release v1.02026-09-29: Release v2.0: updated intro, chap. 1, and biography.
[Background] Scalability is the only DiVincenzo criterion that has not yet been achieved at utility-scale and fault-tolerant levels by any quantum processor. These quantum machines are governed by a classical control system that must scale along with the quantum objects it controls. For the case study of trapped-ion quantum processors, mostly massive room-temperature, rack-based, and non-integrated solutions for its control system are described in literature, which is neither scalable nor efficient. Thus, the control system poses an engineering bottleneck for the scalability of quantum processors. [Objective] Therefore, this study aims to address this gap by proposing a scalable microelectronics-based control architecture blueprint. [Methods] Our method relies on an electronic system-level top-down design methodology, and we illustrate the concepts through a case study. [Results] In this study, we first challenge thestatus quofor the use case of a quantum processor and propose a more pragmatic approach. Second, we present the DiQuNET architecture, which is a system-level architecture for the control of a quantum processor. Finally, we present a case study in which we map the architecture to control a specific quantum processor technology, subsystem, and functionality. [Conclusion] Our proposal is an innately scalable and controldistributed system architecture whose features aim to support the execution of a quantum algorithm at utility-scale levels and embed hardware to support fault-tolerance. It raises the hardware interface of the processor to an algorithm level and opens the door to the joint community and industrial realization of the control system for quantum processors.
[Background] The industrial usefulness of a quantum processor is correlated with its scalability; thus, one of the main focuses of current industrial and academic efforts is to upscale this machine. For trapped-ion quantum processors, some of the most promising scalable architectures require ion transport across surface-segmented traps. Published solutions for the control of ion transport have been mostly developed as bulky, rack-based embedded systems, placed at room temperature outside the vacuum/cryostat chambers, with cables fed in, and with voltages time-multiplexed or broadcast to reach the electrodes of the trap in order to apply the fixed pre-computed raw voltage sets for each fabricated ion trap, where the voltages are tailored to its time- and setup-dependent deposited impurities condition; all of which is neither scalable nor optimally efficient. [Objective] To address this gap, this study proposes a DiQuNET scalable integrated microelectronics solution for ion-transport control. [Methods]We describe the system-level integration strategy and a full engineering development cycle of the device. [Results] This work presents the conception (specification and design) of the ion-transport integrated circuit and the realization (implementation and evaluation) of a proof of concept (TRL 3), which also constitutes a proof of principle of the first DiQuNET compliant integrated circuit. [Conclusion] These results verify and validate the design of an efficient, architecture-scalable, trainable, automated, parametric, and re-configurable proof of concept of the ion-transport integrated circuit. These results support the feasibility, efficiency, and viability potential of the DiQuNET paradigm that uses a distributed set ofautomatamachines to control a quantum processor.
This paper presents a comprehensive review of quantum computing and the technological foundations of quantum processors. Quantum computing represents a transformative computational paradigm that leverages the fundamental principles of quantum mechanics—such as superposition, entanglement, and quantum interference—to solve complex problems that are intractable for classical computers. At the core of this paradigm lies the quantum processor, a specialized hardware system designed to initialize, control, and measure quantum bits (qubits) through precise gate operations and coherent interactions. The survey examines the essential theoretical concepts underlying quantum computation and provides a structured comparison of leading quantum processor platforms. Prominent architectures, including superconducting circuits, trapped-ion systems, and photonic implementations, are analyzed in terms of their physical mechanisms, scalability, coherence properties, and engineering challenges. Each platform offers distinct advantages and faces specific technical limitations related to noise, error correction, and fabrication complexity. In addition to reviewing hardware developments, this study highlights key obstacles in advancing quantum processors toward large-scale, fault-tolerant systems. Issues such as qubit stability, error mitigation, thermal management, and system integration are discussed to present a realistic perspective on current progress. Performance indicators including gate fidelity, coherence time, connectivity, and scalability are used to compare architectural approaches. The objective of this paper is to provide a clear and organized synthesis of recent advancements in quantum computing hardware, thereby offering researchers and practitioners a foundational reference to support continued innovation and development in this rapidly evolving field.
[Background] Ions in an ion trap are among the most promising technologies to implement a quantum processor. This machine is governed by a classic electronic control system, for which we found no systematic electronic system-level approach for its conception, design, implementation, and/or verification. The trapped-ion quantum processor cannot advance its roadmap without an appropriate and fitting electronic control system. To fully enable further advancements in the field, an understanding of the electronic control system as a system of its own and the conception of its electronic system-level description, are due needed. [Objective] Therefore, we want to address the electronic control system of a trapped-ion quantum processor as a system of its own by first identifying its published literature. [Method] For that purpose, we conducted a systematic literature review abiding by the APISSER methodology for systematic literature reviews in engineering, which describes and delimits the reach of this study. [Results] In this paper, we report the results of the study, classify them, and present possible research directions and considerations to be taken in the conception of this system. [Conclusion] This study lays a introductory foundation to grasp the requirements and environment of the electronic control system of a trapped-ion quantum processor. A foundation much needed to leverage further research on this topic by the engineering community. Furthermore, it serves as a checkpoint in time: listing and synthesizing, the existing published body-of-knowledge of this topic within the defined boundaries of our method.
The current approach to building quantum computers relies on a strategy of brute force intervention. Engineers attempt to force fragile quantum states to survive by constantly correcting their errors with external machinery. This method treats the quantum bit, or qubit, as an inherently unstable object that must be propped up. It assumes that if we simply build faster control loops, we can outrun the natural decay of the system. However, this perspective ignores the fundamental cost of fighting nature. Every time we correct an error, we are fighting against the natural tendency of the universe to increase disorder. This fight requires energy, and that energy must go somewhere. The reliance on active error correction creates a vicious cycle of energy consumption. As we add more qubits to the system, the number of errors increases. To fix these errors, we need more control hardware and more processing power. This additional hardware generates heat, which disturbs the sensitive quantum states even more. The more we try to fix the system, the more we disturb it. It is like trying to calm a pool of water by slapping the waves flat. The very act of intervention creates new ripples that require further correction. This scaling problem is not just a matter of engineering difficulty; it is a matter of physics. There is a limit to how fast and how efficiently we can extract entropy, or disorder, from a system. Current architectures are approaching this limit rapidly. We are building systems that require massive cooling infrastructure just to keep the control electronics from melting the qubits. This is not a sustainable path to a useful computer. We need a fundamentally different approach. The brute force method also introduces a complexity bottleneck. The software required to track and correct errors in real-time is becoming impossibly complex. We are trying to simulate a perfect machine using imperfect parts, and the overhead is crushing. The ratio of physical qubits needed to build one logical qubit is skyrocketing. We are spending all our resources on error correction, leaving little for actual computation. This is the definition of a diminishing return. We must recognize that the “active” paradigm is a trap. It lures us in with the promise of total control, but it hides the thermodynamic bill. That bill is coming due, and it is higher than we can pay. We cannot simply scale our way out of this problem with more power. We need to stop fighting the environment and start designing systems that are naturally stable. We need to move from active correction to passive protection.
A quantum machine may solve some complex problems that are intractable for even the most powerful classical computers. By exploiting quantum superposition and entanglement phenomena, quantum algorithms can achieve from polynomial to exponential speed up when compared to their best classical counterparts. A quantum computer will be a part of a heterogeneous, multi-core computer in which a classical processor will interact with several accelerators such as FPGAs, GPUs and also a quantum co-processor. Figure 1 shows the different layers of the quantum computer system stack [1]. Building such a quantum system requires contributions from different fields such as physics, electronics, computer science and computer engineering for addressing the following challenges: i) build scalable quantum chips integrating qubits with long coherence times and high-fidelity operations, ii) develop classical control electronics at possibly cryogenic temperatures and iii) create the microarchitecture as well as the software for quantum computation.