[Background] Ions in an ion trap are among the most promising technologies to implement a quantum processor. This machine is governed by a classic electronic control system, for which we found no systematic electronic system-level approach for its conception, design, implementation, and/or verification. The trapped-ion quantum processor cannot advance its roadmap without an appropriate and fitting electronic control system. To fully enable further advancements in the field, an understanding of the electronic control system as a system of its own and the conception of its electronic system-level description, are due needed. [Objective] Therefore, we want to address the electronic control system of a trapped-ion quantum processor as a system of its own by first identifying its published literature. [Method] For that purpose, we conducted a systematic literature review abiding by the APISSER methodology for systematic literature reviews in engineering, which describes and delimits the reach of this study. [Results] In this paper, we report the results of the study, classify them, and present possible research directions and considerations to be taken in the conception of this system. [Conclusion] This study lays a introductory foundation to grasp the requirements and environment of the electronic control system of a trapped-ion quantum processor. A foundation much needed to leverage further research on this topic by the engineering community. Furthermore, it serves as a checkpoint in time: listing and synthesizing, the existing published body-of-knowledge of this topic within the defined boundaries of our method.
[Background] Ions in an ion trap are among the most promising technologies to implement a quantum processor. This machine is governed by a classic electronic control system, for which we found no systematic electronic system-level approach for its conception, design, implementation, and/or verification. The trapped-ion quantum processor cannot advance its roadmap without an appropriate and fitting electronic control system. To fully enable further advancements in the field, an understanding of the electronic control system as a system of its own and the conception of its electronic system-level description, are due needed. [Objective] Therefore, we want to address the electronic control system of a trapped-ion quantum processor as a system of its own by first identifying its published literature. [Method] For that purpose, we conducted a systematic literature review abiding by the APISSER methodology for systematic literature reviews in engineering, which describes and delimits the reach of this study. [Results] In this paper, we report the results of the study, classify them, and present possible research directions and considerations to be taken in the conception of this system. [Conclusion] This study lays a introductory foundation to grasp the requirements and environment of the electronic control system of a trapped-ion quantum processor. A foundation much needed to leverage further research on this topic by the engineering community. Furthermore, it serves as a checkpoint in time: listing and synthesizing, the existing published body-of-knowledge of this topic within the defined boundaries of our method.
[Background] Scalability is the only DiVincenzo criterion that has not yet been achieved at utility-scale and fault-tolerant levels by any quantum processor. These quantum machines are governed by a classical control system that must scale along with the quantum objects it controls. For the case study of trapped-ion quantum processors, mostly massive room-temperature, rack-based, and non-integrated solutions for its control system are described in literature, which is neither scalable nor efficient. Thus, the control system poses an engineering bottleneck for the scalability of quantum processors. [Objective] Therefore, this study aims to address this gap by proposing a scalable microelectronics-based control architecture blueprint. [Methods] Our method relies on an electronic system-level top-down design methodology, and we illustrate the concepts through a case study. [Results] In this study, we first challenge thestatus quofor the use case of a quantum processor and propose a more pragmatic approach. Second, we present the DiQuNET architecture, which is a system-level architecture for the control of a quantum processor. Finally, we present a case study in which we map the architecture to control a specific quantum processor technology, subsystem, and functionality. [Conclusion] Our proposal is an innately scalable and controldistributed system architecture whose features aim to support the execution of a quantum algorithm at utility-scale levels and embed hardware to support fault-tolerance. It raises the hardware interface of the processor to an algorithm level and opens the door to the joint community and industrial realization of the control system for quantum processors.
[Background] Quantum processors offer a new paradigm for computing which can more accurately model –simulate– the intrinsic quantum nature of microscopic phenomena, can more efficiently compute algorithms with a quantum formulation versus that of their classical formulation, and has been shown to have a higher energy efficiency than classical processors when solving the same problem. Yet, the practical physical implementation of quantum processors is inherently transient, stochastic, and prone to perturbations, which makes the best-performing quantum processor to date to sink in errors before it can get past the 25th circuit gate layer of computation with its 25 quantum bits. A quantum processor promises us benefits, but only if built within a utility-scale size, currently estimated to be of about O(10^6) quantum bits x O(10^9) gate layers, and if we manage to overcome its errors by engineering it fault-tolerantly. After about 30 years in the pursuit of building this machine, we are several orders of magnitude away from usefulness. The challenge is such that this machine potentially boils down to be the largest-scale and most-challenging engineering project that human kind pursues to build during the 21st century. Accordingly, this challenge must be approached with a pragmatic engineering mindset. [Objective] Therefore, this work takes an engineering approach to define a system-level control paradigm for quantum processors, which enables scalability, reliability, usefulness, efficiency, sustainability, and resilience, within the case study of trapped ions. [Methods] In this work, I apply engineering methods, namely, systems and control engineering for the development of a machine. The first step is to clearly understand and describe the problem and what is at stake along the expectations of a current worldwide quantum investment in the US$ O(10^9). To that end, I examine existing prior art through a systematic literature review and conduct numerous interviews of European physicists in order to comprehend the status quo of quantum computing. Second, I use a top-down system-level methodology for the conception of the control system of quantum processors. Finally, I realize a proof of concept for one constituent machine compliant to the system-level proposal. [Results] In light of examining the status quo strategy for quantum computing, I must challenge it and advocate to redirect our efforts towards building this machine as a closed-loop locked-algorithm control system in order to ultimately enable its resilience. First, I propose the top-level ASQP machine and the DiQuNET architecture as novel paradigm for the control of quantum processors. Second, I develop a proof of concept of the first DiQuIC: the ITIC, which is a constituent machine of the DiQuNET system that implements a particular functional task in a trapped-ion quantum processor. [Conclusion] The ASQP is a novel system-level use-case proposal for a quantum processor. The DiQuNET paradigm is a novel system-level proposal for the physical control implementation of the quantum Turing machine. Overall, the control paradigm endows a quantum processor with scalability, reliability, usefulness, sustainability, efficiency, and resilience features. It is a proposal that opens the door to the standardization, the industrial realization, and the human-resources distributed and collaborative development of the control system of quantum processors. Cite this thesis as: S. Castillo, “The DiQuNET Paradigm for the Control of Quantum Processors: The case for Trapped Ions,” Doctoral Thesis, University of Innsbruck, Dept. Mechatron., Innsbruck, Austria, 2026. doi: https://doi.org/10.5281/zenodo.23236620 Thesis information: Grade: 1 (excellent)ISCED-11 Level 8 * Advisors: Prof. T. Northup (UIBK, AT) and Prof. E. Charbon (EPFL, CH)* Evaluator: Prof. R. van Meter (Keio Uni, JP & Editor-in-Chief of IEEE TQE)* Tech-transfer Mentor: Jamie Urquhart (Founder of ARM. Ltd., UK) Revision history: 2026-03-27: First release v1.02026-09-29: Release v2.0: updated intro, chap. 1, and biography.
[Background] The industrial usefulness of a quantum processor is correlated with its scalability; thus, one of the main focuses of current industrial and academic efforts is to upscale this machine. For trapped-ion quantum processors, some of the most promising scalable architectures require ion transport across surface-segmented traps. Published solutions for the control of ion transport have been mostly developed as bulky, rack-based embedded systems, placed at room temperature outside the vacuum/cryostat chambers, with cables fed in, and with voltages time-multiplexed or broadcast to reach the electrodes of the trap in order to apply the fixed pre-computed raw voltage sets for each fabricated ion trap, where the voltages are tailored to its time- and setup-dependent deposited impurities condition; all of which is neither scalable nor optimally efficient. [Objective] To address this gap, this study proposes a DiQuNET scalable integrated microelectronics solution for ion-transport control. [Methods]We describe the system-level integration strategy and a full engineering development cycle of the device. [Results] This work presents the conception (specification and design) of the ion-transport integrated circuit and the realization (implementation and evaluation) of a proof of concept (TRL 3), which also constitutes a proof of principle of the first DiQuNET compliant integrated circuit. [Conclusion] These results verify and validate the design of an efficient, architecture-scalable, trainable, automated, parametric, and re-configurable proof of concept of the ion-transport integrated circuit. These results support the feasibility, efficiency, and viability potential of the DiQuNET paradigm that uses a distributed set ofautomatamachines to control a quantum processor.
This thesis describes the design of a real-time control system for trapped ion quantum computer experiments. It is framed in the context of the QuantumIon project, a project at the University of Waterloo’s Institute for Quantum Computing that aims to provide a scalable, remote-operation ion trap for a wide variety of quantum research without the need for ‘expert’ ion-trap knowledge. The target users span the range of ion-trap researchers,algorithms researchers, performance benchmarking researchers, and quantum simulation researchers.The control system features a user programming language, remote access to a compiling server, a sub-nanosecond time sequencing engine, arbitrary waveform generation for pulse shaping, and fully adjustable internal parameters. This platform affords the user extraordinary flexibility for many research use cases without requiring physical access. High-speed precision timing is achieved through the use of FPGA technology, while internal consistency (necessary for usability by non-experts) is achieved through an abstraction layer approach. Supercomputing-grade network infrastructure is employed to meet the strict timing requirements. An extensive suite of calibration tools and results is available to monitor machine-dependent parameters of the experiment. A sophisticated symbolic algebra system is used to create powerful calculations of precision timing sequences. Extensive automation is employed to remove the need for physical access, thus providing quantum computing to a wide audience. Under this model even the lowest-level control is avail-able to support innovative new designs, while a “library” of pre-defined sequences is also available to leverage “best practice” gates for those wishing rapid results. Finally, the user language itself is designed to be portable, allowing bindings to current popular classical languages such as Matlab and Python, and can be expanded for use in quantum-specific languages such as Cirq, Quill, and QASM .Through this approach the control system for QuantumIon is a flexible, powerful, scalable, and robust platform that is expected to be in use for a long time
This is the second paper in a series of papers providing an overview of different quantum computing hardware platforms from an industrial end-user perspective. It follows our first paper on neutral-atom quantum computing. In the present paper, we provide a survey on the current state-of-the-art in trapped-ion quantum computing, taking up again the perspective of an industrial end-user. To this end, our paper covers, on the one hand, a comprehensive introduction to the physical foundations and mechanisms that play an important role in operating a trapped-ion quantum computer. On the other hand, we provide an overview of the key performance metrics that best describe and characterise such a device's current computing capability. These metrics encompass performance indicators such as qubit numbers, gate times and errors, native gate sets, qubit stability and scalability as well as considerations regarding the general qubit types and trap architectures. In order to ensure that these metrics reflect the current state of trapped-ion quantum computing as accurate as possible, they have been obtained by both an extensive review of recent literature and, more importantly, from discussions with various quantum hardware vendors in the field. We combine these factors and provide - again from an industrial end-user perspective - an overview of what is currently possible with trapped-ion quantum computers, which algorithms and problems are especially suitable for this platform, what are the relevant end-to-end wall clock times for calculations, and what might be possible with future fault-tolerant trapped-ion quantum computers.
Ion trap quantum computers are complex optoelectronic systems that require several electronic subsystems orchestrated to sub-1ns precision, both low-noise and high speed. WUT developed a modular control system in EEM/DIOT form factor called SINARA (Standardised Instrumentation Architecture for Research Applications) [1]. SINARA became the de facto standard in atomic and Molecular laboratories worldwide; a few leading quantum computer manufacturers also use it. Its success, which can be attributed to the open-source, open-hardware licensing model, has significantly advanced the field of quantum computing by providing a reliable and adaptable control system. SINARA was primarily developed for lab applications but recently has been transformed into an industrial form factor (DIOT [5]) because many lab projects have turned into spin-offs and startups.The scaling of quantum computers creates several technological issues. Most topologies are enclosed in a vacuum and use cryogenic temperatures. Future quantum computer architectures need to implement electronic control systems capable of steering hundreds of thousands of electrodes with high precision and relatively high voltage of a few dozen V. Within the framework of the Quantera SIQCI [3] project, a collaborative effort aimed at advancing the field of quantum computing, we are building a demonstrator of such a scalable control system. An essential step of the design process is characterising a standard 180nm high voltage process at temperatures below 10 K. The next step is updating the process PDK and designing the test structures using updated models. This paper presents the requirements for such a control system, the first results of the measurements and the design methodology.Furthermore, this talk will unveil the first coherent operations results performed on ions trapped in the WUT labs using the SINARA system, marking a significant milestone in our system’s practical applications.