This paper presents an overview of the latest research results on integrated, cryogenic-compatible electronics for ion shuttling operation in Trapped-Ion Quantum Computers (TIQCs). Integrated circuit (IC) realization is essential to enable system scaling towards a larger number of qubits. Firstly, we review the specific challenges related to the shuttling operation and ion confinement. Consequently, implications on circuit design of an integrated shuttling controller system on chip (SoC) are discussed. Particularly, among other circuit design parameters, we analyze in detail the requirements on power and area consumption, noise performance, and cryogenic-compatibility. Secondly, we provide an overview on reported discrete solutions, eventually highlighting the need for a dedicated integrated shuttling controller SoC. Hence, state of the art integrated shuttling controller approaches are presented and reviewed. Finally, we conclude the paper with an outlook on promising integrated circuit concepts for shuttling controllers.
This paper presents an overview of the latest research results on integrated, cryogenic-compatible electronics for ion shuttling operation in Trapped-Ion Quantum Computers (TIQCs). Integrated circuit (IC) realization is essential to enable system scaling towards a larger number of qubits. Firstly, we review the specific challenges related to the shuttling operation and ion confinement. Consequently, implications on circuit design of an integrated shuttling controller system on chip (SoC) are discussed. Particularly, among other circuit design parameters, we analyze in detail the requirements on power and area consumption, noise performance, and cryogenic-compatibility. Secondly, we provide an overview on reported discrete solutions, eventually highlighting the need for a dedicated integrated shuttling controller SoC. Hence, state of the art integrated shuttling controller approaches are presented and reviewed. Finally, we conclude the paper with an outlook on promising integrated circuit concepts for shuttling controllers.
This article presents a cryo-BiCMOS system on chip (SoC) designed for single and two-qubit gate operations for quantum computers (QCs) based on beryllium trapped-ions (TIs). Signal generation from 0.7 to 1.6 GHz is supported, covering all microwave transitions in a9Be+QC realization. An integrated 48-kbit waveform memory is implemented for improved two-qubit gate fidelity. The fabricated IC is verified in a 4 K environment with up to 4 qubits, thus enabling quantum processor unit (QPU) cointegration. IC operation up to RT ensures compatibility with future system realizations. Measurements demonstrate qubit state control with an oscillation amplitude of 94% before SPAM correction and Rabi oscillation rate of 172 kHz. Evaluations of long sequences ofσxgates indicate control of the quantum state with high quality. Interaction with one computational zone is possible at a total power consumption of 86 mW translating to 21.5 mW/qubit in the presented measurements. Comparison with the state-of-the-art controller reveals drastic power and form-factor reduction at comparable performance, thus paving the way for a scalable TI platform. The chip is fabricated in a 0.13-μmSiGe BiCMOS technology. To the best of our knowledge, this is the first reported from-scratch system design for TI-based QC concluding with a qubit state manipulation demonstration.
Quantum computers based on trapped ions have approached the point of executing interesting near-term algorithms, but scaling beyond tens of ion qubits will require either increasingly large experiments or integration of control technology. This article presents the design and implementation of a cryogenically compatible dc voltage source incorporated into the substrate beneath the electrodes of an ion trap. An analog switch enables the integrated circuit to reach noise levels similar to those in much larger commercial electronics. These results herald the application of similar designs in future experiments focused on creating scalable or deployable quantum systems.
This paper presents a fully integrated System-on-Chip operating from 295 K down to 4 K, capable of generating 0.7 GHz to 1.5 GHz microwave signals for9Be+trapped-ion quantum computer realizations. The proposed design comprises a three-channel waveform generator with integrated 48 kbit memory to generate arbitrary envelope-modulated control signals while consuming only 94 mW, which in the targeted system results in 1.9 mW/qubit. The IC is capable of driving multiple electrodes as required for all gate operations. The chip was fabricated in a 0.13µm SiGe BiCMOS technology. To the best of the authors’ knowledge, this is the first reported integrated SoC solution for qubit state control in a trapped-ion quantum computer.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
In the pursuit of quantum computing, solid-state quantum systems, particularly superconducting ones, have made remarkable advancements over the past two decades. However, achieving fault-tolerant quantum computing for next-generation applications necessitates the integration of several million qubits, which presents significant challenges in terms of interconnection complexity and latency that are currently unsolvable with state-of-the-art room-temperature control and readout electronics. Recently, cryogenic integrated circuits (ICs), including CMOS radio-frequency ICs and rapid-single-flux-quantum-logic ICs, have emerged as potential alternatives to room-temperature electronics. Unlike their room-temperature counterparts, these ICs are deployed within cryostats to enhance scalability by reducing the number and length of transmission lines. Additionally, operating at cryogenic temperatures can suppress electronic noise and improve qubit control fidelity. However, for CMOS ICs specifically, circuit design uncertainties arise due to a lack of reliable models for cryogenic field effect transistors as well as issues related to severe fickle noises and power dissipation at cryogenic temperatures. This paper provides a comprehensive review of recent research on both types of cryogenic control and readout ICs but primarily focuses on the more mature CMOS technology. The discussion encompasses principles underlying control and readout techniques employed in cryogenic CMOS ICs along with their architectural designs; characterization and modeling approaches for field effect transistors under cryogenic conditions; as well as fundamental concepts pertaining to rapid single flux quantum circuits.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.