Quantum computers based on trapped ions have approached the point of executing interesting near-term algorithms, but scaling beyond tens of ion qubits will require either increasingly large experiments or integration of control technology. This article presents the design and implementation of a cryogenically compatible dc voltage source incorporated into the substrate beneath the electrodes of an ion trap. An analog switch enables the integrated circuit to reach noise levels similar to those in much larger commercial electronics. These results herald the application of similar designs in future experiments focused on creating scalable or deployable quantum systems.
Quantum computers based on trapped ions have approached the point of executing interesting near-term algorithms, but scaling beyond tens of ion qubits will require either increasingly large experiments or integration of control technology. This article presents the design and implementation of a cryogenically compatible dc voltage source incorporated into the substrate beneath the electrodes of an ion trap. An analog switch enables the integrated circuit to reach noise levels similar to those in much larger commercial electronics. These results herald the application of similar designs in future experiments focused on creating scalable or deployable quantum systems.
This paper presents an overview of the latest research results on integrated, cryogenic-compatible electronics for ion shuttling operation in Trapped-Ion Quantum Computers (TIQCs). Integrated circuit (IC) realization is essential to enable system scaling towards a larger number of qubits. Firstly, we review the specific challenges related to the shuttling operation and ion confinement. Consequently, implications on circuit design of an integrated shuttling controller system on chip (SoC) are discussed. Particularly, among other circuit design parameters, we analyze in detail the requirements on power and area consumption, noise performance, and cryogenic-compatibility. Secondly, we provide an overview on reported discrete solutions, eventually highlighting the need for a dedicated integrated shuttling controller SoC. Hence, state of the art integrated shuttling controller approaches are presented and reviewed. Finally, we conclude the paper with an outlook on promising integrated circuit concepts for shuttling controllers.
One of the most formidable challenges of scaling up quantum computers is that of control-signal delivery.Today's small-scale quantum computers typically connect each qubit to one or more separate external signal sources.This approach is not scalable due to the input/output (I/O) limitations of the qubit chip, necessitating the integration of control electronics.However, it is no small feat to shrink control electronics into a small package that is compatible with qubit-chip fabrication and operational constraints without sacrificing performance.This so-called "wiring challenge" is likely to impact the development of more powerful quantum computers even in the near term.In this paper, we address the wiring challenge of trapped-ion quantum computers.We describe a control architecture called WISE (Wiring using Integrated Switching Electronics), which significantly reduces the I/O requirements of ion-trap quantum computing chips without compromising performance.Our method relies on judiciously integrating simple switching electronics into the ion-trap chip-in a way that is compatible with its fabrication and operation constraints-while the complex electronics remain external.To demonstrate its power, we describe how the WISE architecture can be used to operate a fully connected 1000-qubit trapped-ion quantum computer using approximately 200 signal sources at a speed of approximately 40-2600 quantum gate layers per second.
[Background] The industrial usefulness of a quantum processor is correlated with its scalability; thus, one of the main focuses of current industrial and academic efforts is to upscale this machine. For trapped-ion quantum processors, some of the most promising scalable architectures require ion transport across surface-segmented traps. Published solutions for the control of ion transport have been mostly developed as bulky, rack-based embedded systems, placed at room temperature outside the vacuum/cryostat chambers, with cables fed in, and with voltages time-multiplexed or broadcast to reach the electrodes of the trap in order to apply the fixed pre-computed raw voltage sets for each fabricated ion trap, where the voltages are tailored to its time- and setup-dependent deposited impurities condition; all of which is neither scalable nor optimally efficient. [Objective] To address this gap, this study proposes a DiQuNET scalable integrated microelectronics solution for ion-transport control. [Methods]We describe the system-level integration strategy and a full engineering development cycle of the device. [Results] This work presents the conception (specification and design) of the ion-transport integrated circuit and the realization (implementation and evaluation) of a proof of concept (TRL 3), which also constitutes a proof of principle of the first DiQuNET compliant integrated circuit. [Conclusion] These results verify and validate the design of an efficient, architecture-scalable, trainable, automated, parametric, and re-configurable proof of concept of the ion-transport integrated circuit. These results support the feasibility, efficiency, and viability potential of the DiQuNET paradigm that uses a distributed set ofautomatamachines to control a quantum processor.
Trapped-ion quantum computers based on the quantum charge-coupled device architecture require on the order of ten trap electrodes per qubit, making the number of vacuum feedthroughs a bottleneck at the system scale. Time-division multiplexed (TDM)-based voltage control for trap electrodes provides a natural route to alleviate this constraint. However, previous studies have been limited to architectural proposals for static trap-potential compensation and room-temperature demonstrations of dynamic-electrode control, leaving cryogenic operation of TDM-based voltage control for static and dynamic electrodes experimentally unexplored. In this study, we develop and cryogenically validate TDM-based voltage control schemes for two distinct electrode classes. For static electrodes used in trap-potential compensation, we implement a 32-channel demultiplexed system operating at approximately 27~K, achieving an effective voltage update rate of 37.5~kHz with an output range of ±10V per channel. For dynamic electrodes used in ion operations, such as shuttling, we implement a four-channel demultiplexed system operating at approximately 14~K, achieving an effective voltage update rate of 1~MHz with a comparable output range. These results establish TDM-based voltage control as a practical approach for both electrode classes, providing a path for mitigating the vacuum feedthrough bottleneck in scalable trapped-ion quantum processors.
We report on our systems engineering activities concerning cryogenic CMOS electronics as building blocks for scalable quantum computers. Following the V-model of engineering, the topic is approached both in top-down and in bottom-up fashion. We show the main results from the top-down study using system modeling and simulations. In a bottom-up fashion, a prototype chip was designed and implemented in a commercial 65nm CMOS process. The chip contains a DC digital-to-analog-converter (DC-DAC) and a Pulse-DAC as building blocks for an integrated quantum bit control. The DC-DAC is able to tune a qubit into its operating point. The Pulse-DAC generates pulse patterns with 250MHz sampling frequency to perform gate operations on a qubit.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.