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Conference on Design of Circuits and Integrated Systems

A 1.15 mW SiGe BiCMOS Cryogenic LNA for Superconducting Qubit Readout with 4.5 K Noise Temperature From 4 to 9 GHz

Aleksei Nerushenko, Roc Berenguer, Alvaro Urain, Héctor Solar

Published Nov 26, 2025• 1 citation

Abstract

This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies$0.252 \text{mm}^{2}$. Post-layout simulations confirm input/output S-parameter matching better than$-10 \text{dB}, 41-44 \text{dB}$gain with$<3 \text{dB}$ripple,$<5 \mathrm{K}$noise temperature across$4-9 \text{GHz}$, and a worst-case OP1 dB compression point of$\mathbf{- 1 9. 9 6. 6 d B m}$. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.

DOI: 10.1109/dcis67520.2025.11281903

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This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies

0.252 \text{mm}^{2}

. Post-layout simulations confirm input/output S-parameter matching better than

-10 \text{dB}, 41-44 \text{dB}

gain with

<3 \text{dB}

ripple,

<5 \mathrm{K}

noise temperature across

4-9 \text{GHz}

, and a worst-case OP1 dB compression point of

\mathbf{- 1 9. 9 6. 6 d B m}

. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.

In this article, a cryogenically cooled SiGe BiCMOS integrated circuit is described and used to achieve >98% readout fidelity when measuring the state of a superconducting transmon qubit coupled to a 6.5-GHz resonant cavity. The circuit employs homodyne detection and uses a novel local oscillator chopping approach to reduce the effects of LO-RF feedthrough in the presence of a high-gain LNA. At 6 mW, the integrated circuit is employed to demonstrate comparable fidelity to a standard HEMT-amplifier-based readout setup, when preceded by a Josephson parametric amplifier with

\geq \sim 18

dB of power gain. In addition, this performance is achieved with the IC consuming less power than the commercial HEMT LNA used in the standard readout setup. To the best of the authors’ knowledge, this is the first demonstration of high-fidelity state readout of superconducting qubits without a standalone cryogenic semiconductor LNA. This demonstration represents an important step in the realization of fully integrated large-scale cryogenic qubit control systems.

The cryogenic indium phosphide (InP) high-electron-mobility transistor (HEMT) low-noise amplifier (LNA) is used for the readout amplification of qubits at

4

K where cooling capabilities are limited implying that the dc power of the active circuits is an essential design constraint. In this article, the RF and noise performance of the InP HEMT under ultralow-power (ULP) operation at

4

K has been characterized. The small-signal and noise parameter model of the InP HEMT was extracted down to 1

\mu

W. The tradeoff between noise performance and dc power consumption was analyzed in terms of the drain current and drain voltage. A 4–6 GHz hybrid cryogenic HEMT LNA designed for qubit readout and optimized for lowest noise below

1

mW dc power consumption was fabricated. The measured performance of the LNA at

4

K attained 23.1 dB average gain and 2.0 K average noise temperature at 200

\mu

W dc power.

A SiGe BiCMOS cryogenic direct-conversion receiver operating at 4 K is presented that demonstrates high-fidelity readout of a transmon qubit. Notably, at 6 mW, this design demonstrates a readout fidelity greater than 98% in

\mathbf{1}\ \mu \mathbf{s}

when preceded by a Josephson parametric amplifier with a gain of 15–18 dB. To the best of the authors' knowledge, this is the first system that entirely replaces an InP-HEMT LNA-based receiver chain with a silicon readout integrated circuit. This demonstration represents an important step in the realization of fully integrated, large-scale cryogenic qubit control systems.

This work presents the design and optimization of a low-noise amplifier (LNA) for qubit readout in cryogenic environments of 3 − 4 K. The proposed LNA achieves wide bandwidth (4 GHz), high gain (47.0 dB), and sufficient linearity (IIP 3 = −34 dBm), while maintaining power consumption below 50 mW, making it suitable for integration into quantum computing systems. The amplifier is based on multi-stage cascode architectures with integrated inductances and impedance-matching techniques to optimize performance for a centre frequency of 5 GHz. While the results demonstrate good performance, there is still room for improvement in the S11parameter and the noise figure (NF ), which could benefit from a more refined transformer model. The proposed design represents a significant step toward integrating high-efficiency readout electronics into quantum computing architectures.

A cryogenic low-voltage, broadband low-noise amplifier(LNA) has been designed for qubit state readout systems. The proposed LNA utilizes passive components for noise cancellation. A tri-coupled transformer is utilized to simultaneously achieve broadband input impedance matching and noise matching. Additionally, it incorporates capacitive feedback and an in-phase transformer to effectively cancel noise. Implemented in 28-nm bulk CMOS technology and verified at 10 K, the LNA achieves a maximum gain of 26.7 dB, a −3-dB bandwidth of 2.2 GHz, a lowest noise temperature (NT) of 25 K, a power consumption of 4.05 mW at 0.6-V supply voltage, and a figure of merit (FoM) of 0.12 dB/mW/ph, which is comparable with the recent works.

Low-power cryogenic LNAs are of interest in future large-scale quantum computing where available cooling capability limits the number of active circuits. We present a comparison of small-signal noise models between two different 100-nm gate-length InP HEMTs at 4 K. The HEMTs were tested in the first stage of a three-stage hybrid cryogenic 4-6 GHz LNA operating at 100

-\mu

W dc power. The better performing cryogenic LNA exhibited 23.2 dB average gain, 2.0 K average noise temperature, and -55dBm input 1-dB compression point. The enhanced LNA performance was attributed to the improved transconductance of the first-stage HEMT. To the authors’ knowledge, this is the lowest noise reported to date for a 100

-\mu

W transistor-based LNA aimed for qubit readout.