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International Conference on Microwave and Millimeter Wave Technology (ICMMT)

A 4–8 GHz GaAs LNA with 15K Noise Temperature for Superconducting Qubit Readout

Zhe Wang, Ruihao Yin, Hua Chen

Published May 1, 2026• 0 citations
Publisher
DOI
10.1109/icmmt69626.2026.11678339

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This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies$0.252 \text{mm}^{2}$. Post-layout simulations confirm input/output S-parameter matching better than$-10 \text{dB}, 41-44 \text{dB}$gain with$<3 \text{dB}$ripple,$<5 \mathrm{K}$noise temperature across$4-9 \text{GHz}$, and a worst-case OP1 dB compression point of$\mathbf{- 1 9. 9 6. 6 d B m}$. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.

Conference on Design of Circuits and Integrated Systems•Nov 26, 2025•1 citation
The measurement of the fast-increasing number of qubits necessitates the use of a large number of specialized cryogenic low-noise amplifiers (LNAs).). This work presents a broadband LNA designed with discrete GaAs HEMT components which operate well at ~3.6 K temperature. The dual-frequency optimum noise matching network and output matching elements of the first stage were employed to optimize the equivalent noise temperature (NT) and the input return loss in a wideband. Measurement results at 3.6 K ambient temperature show that the LNA achieved an equivalent NT of30 dB in the 3.5 GHz to 7.5 GHz band with a minimum of 5 Kelvin at ~6.5 GHz. The best visibility of ~0.891 is achieved when using the LNA to observe a superconducting transmon qubit without using a JPA.
Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNA) for qubit readout. Here we present a C-Band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on 150 nm GaAs pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance match to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third-stage enhances the overall stability. Moreover, the pHEMT-self bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a 5 K equivalent noise temperature and an average gain of 40 dB. We further benchmark this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.
This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies0.252mm20.252 \text{mm}^{2}0.252mm2. Post-layout simulations confirm input/output S-parameter matching better than−10dB,41−44dB-10 \text{dB}, 41-44 \text{dB}−10dB,41−44dBgain with<3dB<3 \text{dB}<3dBripple,<5K<5 \mathrm{K}<5Knoise temperature across4−9GHz4-9 \text{GHz}4−9GHz, and a worst-case OP1 dB compression point of−19.96.6dBm\mathbf{- 1 9. 9 6. 6 d B m}−19.96.6dBm. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.