In this article, a cryogenically cooled SiGe BiCMOS integrated circuit is described and used to achieve >98% readout fidelity when measuring the state of a superconducting transmon qubit coupled to a 6.5-GHz resonant cavity. The circuit employs homodyne detection and uses a novel local oscillator chopping approach to reduce the effects of LO-RF feedthrough in the presence of a high-gain LNA. At 6 mW, the integrated circuit is employed to demonstrate comparable fidelity to a standard HEMT-amplifier-based readout setup, when preceded by a Josephson parametric amplifier with
≥∼18dB of power gain. In addition, this performance is achieved with the IC consuming less power than the commercial HEMT LNA used in the standard readout setup. To the best of the authors’ knowledge, this is the first demonstration of high-fidelity state readout of superconducting qubits without a standalone cryogenic semiconductor LNA. This demonstration represents an important step in the realization of fully integrated large-scale cryogenic qubit control systems.
This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies
0.252mm2. Post-layout simulations confirm input/output S-parameter matching better than
−10dB,41−44dBgain with
<3dBripple,
<5Knoise temperature across
4−9GHz, and a worst-case OP1 dB compression point of
−19.96.6dBm. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.
This thesis proposes a pathway to realizing large-scale quantum computing integrated circuits based on the monolithic integration of high-temperature (1–4 K) semiconductor qubits with their associated control and readout circuitry. High-frequency device characterization was performed on production 22-nm FDSOI technology at room and cryogenic temperatures (down to 3.3 K) to inform a cryogenic circuit design methodology in the absence of low-temperature device models. The methodology was demonstrated with a TIA qubit-readout chain that was, for the first time, monolithically integrated with electron and hole quantum dot structures. The prospects of FDSOI SiGe BiCMOS technology would enable similar integration with higher performance HBT devices. As a first step, design of a 240-GHz direct conversion I-Q receiver is showcased in 55-nm SiGe BiCMOS, intended for frequency-division multiplexed readout of many qubits. The measured IF-bandwidth of 59 GHz makes it suitable for high data-rate communication and large-scale quantum processors.
In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.
Engineering research in quantum computing is geared towards building a ”useful” quantum computer; usefulness here refers to the capability of solving computation problems that hold significant value in commercial applications, but are currently impossible to do in reasonable time-frames using classical algorithms. This is fundamentally a problem of scale – problems that can be solved by few-qubit processors can also be readily simulated by classical supercomputers in realistic time-frames, but as these problems grow in complexity, quantum computers are believed to be able to provide an exponential speedup over their classical counterparts, the so-called quantum advantage. However, scaling quantum computers presents many challenges due to the need to perform complex signal control and data processing at nanosecond time scales on fragile quantum systems that need stringent degrees of isolation from the environment for the computations to be carried out with high fidelity. Some of the most promising implementations of experimental-grade quantum computers are maintained in cryogenic environments due to the fact that at low enough temperatures noise processes due to random thermal excitations can be minimized. However, the control and measurement of quantum processors is currently done by systems at room temperature, whose connections to the cryogenic environment present thermal loading that will need to be addressed as these processors scale and their IO requirements to co-processors grow in complexity. As such, one possible path to scaling co-processing capabilities without compromising the quantum processor’s performance is the partial or complete integration of the co-processor in the cryo-environment. Several works describe systems that aim to do just that; and ”Cryo-CMOS” has become an important research subspace. This thesis aims to add to the current advancements in this field, specifically in the area of qubit measurements. It culminates in the implementation of a radio receiver that leverages the advantages of BiCMOS technology in cryo-environments to measure the state of a superconducting transmon-based qubit while strapped to a 4K stage in a dilution refrigerator. Critically, we demonstrate that low-noise amplification, down-conversion, and demodulation can all be done in the cryo-environment on a constrained power budget, with high fidelity comparable to a state-of-the-art (InP-HEMT LNA-based) qubit readout system, when preceded by a high-gain, quantum-noise-limited Josephson parametric amplifier.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at
3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of
10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at
3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be
<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion,
4 K receiver for qubit readout that achieves
>1.9GHz of IF bandwidth with
>50 dB conversion gain and
0.7 dB NF while consuming only
17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing
3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.