A SiGe BiCMOS cryogenic direct-conversion receiver operating at 4 K is presented that demonstrates high-fidelity readout of a transmon qubit. Notably, at 6 mW, this design demonstrates a readout fidelity greater than 98% in
1 μswhen preceded by a Josephson parametric amplifier with a gain of 15–18 dB. To the best of the authors' knowledge, this is the first system that entirely replaces an InP-HEMT LNA-based receiver chain with a silicon readout integrated circuit. This demonstration represents an important step in the realization of fully integrated, large-scale cryogenic qubit control systems.
This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies
0.252mm2. Post-layout simulations confirm input/output S-parameter matching better than
−10dB,41−44dBgain with
<3dBripple,
<5Knoise temperature across
4−9GHz, and a worst-case OP1 dB compression point of
−19.96.6dBm. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.
This thesis proposes a pathway to realizing large-scale quantum computing integrated circuits based on the monolithic integration of high-temperature (1–4 K) semiconductor qubits with their associated control and readout circuitry. High-frequency device characterization was performed on production 22-nm FDSOI technology at room and cryogenic temperatures (down to 3.3 K) to inform a cryogenic circuit design methodology in the absence of low-temperature device models. The methodology was demonstrated with a TIA qubit-readout chain that was, for the first time, monolithically integrated with electron and hole quantum dot structures. The prospects of FDSOI SiGe BiCMOS technology would enable similar integration with higher performance HBT devices. As a first step, design of a 240-GHz direct conversion I-Q receiver is showcased in 55-nm SiGe BiCMOS, intended for frequency-division multiplexed readout of many qubits. The measured IF-bandwidth of 59 GHz makes it suitable for high data-rate communication and large-scale quantum processors.
Millions of qubits need to be employed in a quantum computer to achieve a fault-tolerant quantum operation. To reduce the complexity in such a large-scale system, the control and readout circuitries have been proposed to be placed at the 4 K stage of dilution refrigerators [1]. CMOS technology is commonly used to leverage its scaling to enable large integration of control and readout circuitries with qubits. However, the high-fidelity readout operations require low noise amplifiers (LNAs) with a noise temperature of a few Kelvins. This necessitates the usage of HEMT and parametric amplifiers [2]. Recently reported CMOS LNAs are still far away from attaining such good performance [3–5]. Thus, this is one of the greatest challenges on the way to the fully integrated CMOS readout. Additionally, due to the limited cooling power of dilution refrigerators, low-power solutions are needed for achieving a very good noise performance at 4 K. This paper presents a 28 nm CMOS LNA for qubit readout, which achieves an order of magnitude power reduction compared to its CMOS counterparts while still providing a similar good noise Figure (NF) performance at 4 K.
Engineering research in quantum computing is geared towards building a ”useful” quantum computer; usefulness here refers to the capability of solving computation problems that hold significant value in commercial applications, but are currently impossible to do in reasonable time-frames using classical algorithms. This is fundamentally a problem of scale – problems that can be solved by few-qubit processors can also be readily simulated by classical supercomputers in realistic time-frames, but as these problems grow in complexity, quantum computers are believed to be able to provide an exponential speedup over their classical counterparts, the so-called quantum advantage. However, scaling quantum computers presents many challenges due to the need to perform complex signal control and data processing at nanosecond time scales on fragile quantum systems that need stringent degrees of isolation from the environment for the computations to be carried out with high fidelity. Some of the most promising implementations of experimental-grade quantum computers are maintained in cryogenic environments due to the fact that at low enough temperatures noise processes due to random thermal excitations can be minimized. However, the control and measurement of quantum processors is currently done by systems at room temperature, whose connections to the cryogenic environment present thermal loading that will need to be addressed as these processors scale and their IO requirements to co-processors grow in complexity. As such, one possible path to scaling co-processing capabilities without compromising the quantum processor’s performance is the partial or complete integration of the co-processor in the cryo-environment. Several works describe systems that aim to do just that; and ”Cryo-CMOS” has become an important research subspace. This thesis aims to add to the current advancements in this field, specifically in the area of qubit measurements. It culminates in the implementation of a radio receiver that leverages the advantages of BiCMOS technology in cryo-environments to measure the state of a superconducting transmon-based qubit while strapped to a 4K stage in a dilution refrigerator. Critically, we demonstrate that low-noise amplification, down-conversion, and demodulation can all be done in the cryo-environment on a constrained power budget, with high fidelity comparable to a state-of-the-art (InP-HEMT LNA-based) qubit readout system, when preceded by a high-gain, quantum-noise-limited Josephson parametric amplifier.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at
3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of
10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at
3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be
<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion,
4 K receiver for qubit readout that achieves
>1.9GHz of IF bandwidth with
>50 dB conversion gain and
0.7 dB NF while consuming only
17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing
3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.