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IEEE Microwave and Wireless Technology Letters

A 7.3–9.5-GHz Cryogenic LNA Based on Passive Noise Cancellation for Qubit State Readout

Yaoyu Li, Yanshu Guo, Tian Tian, Wenqiang Huang, Zhihua Wang, Yuanjin Zheng, Hanjun Jiang

Published May 26, 2025• 2 citations
Publisher

Abstract

A cryogenic low-voltage, broadband low-noise amplifier(LNA) has been designed for qubit state readout systems. The proposed LNA utilizes passive components for noise cancellation. A tri-coupled transformer is utilized to simultaneously achieve broadband input impedance matching and noise matching. Additionally, it incorporates capacitive feedback and an in-phase transformer to effectively cancel noise. Implemented in 28-nm bulk CMOS technology and verified at 10 K, the LNA achieves a maximum gain of 26.7 dB, a −3-dB bandwidth of 2.2 GHz, a lowest noise temperature (NT) of 25 K, a power consumption of 4.05 mW at 0.6-V supply voltage, and a figure of merit (FoM) of 0.12 dB/mW/ph, which is comparable with the recent works.

DOI
10.1109/lmwt.2025.3570110

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A cryogenic low-voltage, broadband low-noise amplifier(LNA) has been designed for qubit state readout systems. The proposed LNA utilizes passive components for noise cancellation. A tri-coupled transformer is utilized to simultaneously achieve broadband input impedance matching and noise matching. Additionally, it incorporates capacitive feedback and an in-phase transformer to effectively cancel noise. Implemented in 28-nm bulk CMOS technology and verified at 10 K, the LNA achieves a maximum gain of 26.7 dB, a −3-dB bandwidth of 2.2 GHz, a lowest noise temperature (NT) of 25 K, a power consumption of 4.05 mW at 0.6-V supply voltage, and a figure of merit (FoM) of 0.12 dB/mW/ph, which is comparable with the recent works.
This work introduces a broadband cryogenic receiver for scalable multiplexed readout of qubits. The receiver utilizes a double quadrature architecture with amplitude and phase error suppression. The hybrid poly-phase filter (PPF) is applied in the architecture to further reduce the input amplitude and phase errors at the radio frequency (RF) end, enhancing the circuit's overall error vector magnitude (EVM). To address the issue of wide bandwidth (BW) for qubit expansion, a low noise amplifier (LNA) with broadband input and noise matching and an improved four-input intermediate frequency amplifier (IF-AMP) with a resistance feedback structure are proposed, achieving a broadband gain response with high flatness. The chip has been designed in standard 55 nm CMOS technology. The LNA achieves a measured power gain of 27.4 dB at 5 GHz with a -3 dB BW of 5.2 GHz at 6 K. Across the entire band of interest, the measured noise figure (NF) deviates by just 0.15 dB from the minimum noise figure (NFmin) and less than 2 dB at 300K, while the measured cryogenic NF falls within the range of 0.79-1 dB. The LNA consumes only 5.5 mW from a 1.2 V supply. Simulation results of the designed receiver indicate that it delivers an average gain of 49.5 dB with a -3 dB BW of 2.4 GHz and an image rejection ratio (IRR) exceeding 40 dB at 300 K.
This letter presents an ultrawideband cryogenic low-noise amplifier (LNA) with current reuse and stacked inverter-based input-referred noise (IRN) cancellation in 40-nm CMOS. The first stage utilizes an IRN reduction high-QQQgate inductor with current reuse, a stacked inverter-based shunt-resistive feedback input stage, and a cryogenically aware back-gate biasing technique to regulate the threshold voltage under cryogenic operation. The second stage is the common-source (CS) main amplifier, followed by a cascode current-reuse auxiliary amplifier to suppress the channel thermal noise of the main amplifier. The third stage is the current-reuse CS inverter-based postamplifier buffer stage. At 4 K, the LNA achieves a measured peak gain (S21{S} _{21}S21​) of 37 dB, with a large 3-dB bandwidth (BW) from 0.15 to 8 GHz and aNFminof 0.4 dB at 3.2 GHz underPDC{P} _{\mathrm {DC}}PDC​of 13.2 mW. To our knowledge, the proposed LNA achieves the BW bandwidth and the figure of merit (FoM) among the highest compared to published CMOS LNAs operating at 4 K. The proposed LNA is suitable for both spin and superconducting qubit readout.
This work presents the design and optimization of a low-noise amplifier (LNA) for qubit readout in cryogenic environments of 3 − 4 K. The proposed LNA achieves wide bandwidth (4 GHz), high gain (47.0 dB), and sufficient linearity (IIP 3 = −34 dBm), while maintaining power consumption below 50 mW, making it suitable for integration into quantum computing systems. The amplifier is based on multi-stage cascode architectures with integrated inductances and impedance-matching techniques to optimize performance for a centre frequency of 5 GHz. While the results demonstrate good performance, there is still room for improvement in the S11parameter and the noise figure (NF ), which could benefit from a more refined transformer model. The proposed design represents a significant step toward integrating high-efficiency readout electronics into quantum computing architectures.
The measurement of the fast-increasing number of qubits necessitates the use of a large number of specialized cryogenic low-noise amplifiers (LNAs).). This work presents a broadband LNA designed with discrete GaAs HEMT components which operate well at ~3.6 K temperature. The dual-frequency optimum noise matching network and output matching elements of the first stage were employed to optimize the equivalent noise temperature (NT) and the input return loss in a wideband. Measurement results at 3.6 K ambient temperature show that the LNA achieved an equivalent NT of30 dB in the 3.5 GHz to 7.5 GHz band with a minimum of 5 Kelvin at ~6.5 GHz. The best visibility of ~0.891 is achieved when using the LNA to observe a superconducting transmon qubit without using a JPA.
This article presents a cryogenic CMOS receiver operating across 4.7–7.9 GHz for frequency-division multiplexing (FDM) quantum state readout. The designed receiver employs a double quadrature (DQ) architecture and a hybrid poly-phase filter (PPF) is proposed to achieve an impressive image rejection ratio (IRR) to meet the 99.99% higher fidelity requirements in quantum error correction (QEC). In addition, gain tuning at different stages of the low noise amplifier (LNA) facilitates a broadband gain and flatness, while the subsequent receiver chains of a broadband mixer and an improved four-input intermediate frequency amplifier (IF-AMP) provide further gain compensation. Fabricated with a standard 55-nm CMOS technology, the LNA achieves a measured power gain of 27.4 dB, with a −3-dB bandwidth (BW) of 5.2 GHz at 6 K. The measured cryogenic noise figure (NF) ranges from 0.79 to 1 dB consuming merely 5.5 mW from a 1.2-V supply. Overall receiver measurements demonstrate a peak gain of 48.2 dB, a −5-dB flatness of 3.2 GHz, and an IRR that exceeds 40 dB at 6 K. These results demonstrate the receiver’s capacity for high-fidelity qubits’ state readout.
This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies0.252mm20.252 \text{mm}^{2}0.252mm2. Post-layout simulations confirm input/output S-parameter matching better than−10dB,41−44dB-10 \text{dB}, 41-44 \text{dB}−10dB,41−44dBgain with<3dB<3 \text{dB}<3dBripple,<5K<5 \mathrm{K}<5Knoise temperature across4−9GHz4-9 \text{GHz}4−9GHz, and a worst-case OP1 dB compression point of−19.96.6dBm\mathbf{- 1 9. 9 6. 6 d B m}−19.96.6dBm. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.