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International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

Design of a Low-Noise Amplifier for Qubit Readout

Gabriel López-Pinar, Uxua Esteban Eraso, Santiago Celma, Carlos Sánchez‐Azqueta

Published Jul 7, 2025• 1 citation
Publisher

Abstract

This work presents the design and optimization of a low-noise amplifier (LNA) for qubit readout in cryogenic environments of 3 − 4 K. The proposed LNA achieves wide bandwidth (4 GHz), high gain (47.0 dB), and sufficient linearity (IIP 3 = −34 dBm), while maintaining power consumption below 50 mW, making it suitable for integration into quantum computing systems. The amplifier is based on multi-stage cascode architectures with integrated inductances and impedance-matching techniques to optimize performance for a centre frequency of 5 GHz. While the results demonstrate good performance, there is still room for improvement in the S11parameter and the noise figure (NF ), which could benefit from a more refined transformer model. The proposed design represents a significant step toward integrating high-efficiency readout electronics into quantum computing architectures.

DOI
10.1109/smacd65553.2025.11092075

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This work presents the design and optimization of a low-noise amplifier (LNA) for qubit readout in cryogenic environments of 3 − 4 K. The proposed LNA achieves wide bandwidth (4 GHz), high gain (47.0 dB), and sufficient linearity (IIP 3 = −34 dBm), while maintaining power consumption below 50 mW, making it suitable for integration into quantum computing systems. The amplifier is based on multi-stage cascode architectures with integrated inductances and impedance-matching techniques to optimize performance for a centre frequency of 5 GHz. While the results demonstrate good performance, there is still room for improvement in the S11parameter and the noise figure (NF ), which could benefit from a more refined transformer model. The proposed design represents a significant step toward integrating high-efficiency readout electronics into quantum computing architectures.
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A cryogenic low-voltage, broadband low-noise amplifier(LNA) has been designed for qubit state readout systems. The proposed LNA utilizes passive components for noise cancellation. A tri-coupled transformer is utilized to simultaneously achieve broadband input impedance matching and noise matching. Additionally, it incorporates capacitive feedback and an in-phase transformer to effectively cancel noise. Implemented in 28-nm bulk CMOS technology and verified at 10 K, the LNA achieves a maximum gain of 26.7 dB, a −3-dB bandwidth of 2.2 GHz, a lowest noise temperature (NT) of 25 K, a power consumption of 4.05 mW at 0.6-V supply voltage, and a figure of merit (FoM) of 0.12 dB/mW/ph, which is comparable with the recent works.
The cryogenic indium phosphide (InP) high-electron-mobility transistor (HEMT) low-noise amplifier (LNA) is used for the readout amplification of qubits at444K where cooling capabilities are limited implying that the dc power of the active circuits is an essential design constraint. In this article, the RF and noise performance of the InP HEMT under ultralow-power (ULP) operation at444K has been characterized. The small-signal and noise parameter model of the InP HEMT was extracted down to 1μ\muμW. The tradeoff between noise performance and dc power consumption was analyzed in terms of the drain current and drain voltage. A 4–6 GHz hybrid cryogenic HEMT LNA designed for qubit readout and optimized for lowest noise below111mW dc power consumption was fabricated. The measured performance of the LNA at444K attained 23.1 dB average gain and 2.0 K average noise temperature at 200μ\muμW dc power.
Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNAs) for qubit readout. Here we presented a C-band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on a 150 nm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance matching to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third stages enhances the overall stability. Moreover, the pHEMT self-bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only a single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a minimum noise temperature of 4 K and an average gain of 40 dB. We further benchmarked this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.
Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNA) for qubit readout. Here we present a C-Band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on 150 nm GaAs pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance match to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third-stage enhances the overall stability. Moreover, the pHEMT-self bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a 5 K equivalent noise temperature and an average gain of 40 dB. We further benchmark this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.
This work introduces a broadband cryogenic receiver for scalable multiplexed readout of qubits. The receiver utilizes a double quadrature architecture with amplitude and phase error suppression. The hybrid poly-phase filter (PPF) is applied in the architecture to further reduce the input amplitude and phase errors at the radio frequency (RF) end, enhancing the circuit's overall error vector magnitude (EVM). To address the issue of wide bandwidth (BW) for qubit expansion, a low noise amplifier (LNA) with broadband input and noise matching and an improved four-input intermediate frequency amplifier (IF-AMP) with a resistance feedback structure are proposed, achieving a broadband gain response with high flatness. The chip has been designed in standard 55 nm CMOS technology. The LNA achieves a measured power gain of 27.4 dB at 5 GHz with a -3 dB BW of 5.2 GHz at 6 K. Across the entire band of interest, the measured noise figure (NF) deviates by just 0.15 dB from the minimum noise figure (NFmin) and less than 2 dB at 300K, while the measured cryogenic NF falls within the range of 0.79-1 dB. The LNA consumes only 5.5 mW from a 1.2 V supply. Simulation results of the designed receiver indicate that it delivers an average gain of 49.5 dB with a -3 dB BW of 2.4 GHz and an image rejection ratio (IRR) exceeding 40 dB at 300 K.