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Quantum Computing, Communication, and Simulation

Superconducting 2.5D interposer for quantum processors

Hongyu Li, Adrian Nugraha Utama, Naga Manikanta Kommanaboina, Norhanani Binte Jaafar, Ding Huang, Yiyu Zhang, Yong Chyn Ng, Kuan Eng Johnson Goh, Manas Mukherjee

Published Mar 19, 2025• 1 citation
Publisher

Abstract

With the increasing number of solid state-based qubits and functionality, superconducting interposer provides a platform for integration of qubit and control devices. Superconducting 2.5D interposer has been developed and fabricated in CMOS compatible advance packaging line. This development work leveraged the mature semiconductor technology. Transition temperature and critical current has been measured and reported in this paper.

DOI
10.1117/12.3043199

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With the increasing number of solid state-based qubits and functionality, superconducting interposer provides a platform for integration of qubit and control devices. Superconducting 2.5D interposer has been developed and fabricated in CMOS compatible advance packaging line. This development work leveraged the mature semiconductor technology. Transition temperature and critical current has been measured and reported in this paper.
An advanced quantum processor requires millions of qubits but is at present limited in scalability due to limitations in the wiring of qubits. A 2.5D silicon (Si) interposer provides an attractive solution in enabling the scalability of the qubit devices. However, some qubits, like the superconducting qubits and solid-state spin-orbit qubits, operate in cryogenic temperatures below 1K. Copper (Cu) interconnects in conventional Si interposers are not superconductive in nature. As such, these metals contribute to losses and result in resistive heating, which can undesirably increase the temperature of the qubits during operation. This paper reports the full demonstration and electrical characterization of a cryogenic interposer with superconducting interconnects and TSV, using CMOS compatible materials like Aluminium (Al), Titanium (Ti), Titanium Nitride (TiN) and Tantalum (Ta).
2.5D packaging improves performance and power efficiency due to shorter connectivity distance, enhances signal integrity owing to reduce wiring lengths and higher integration densities. Current technologies cannot provide an integration technique that can handle thousands of single flux quantum devices required for operation. Other criteria include high integration density per chip, a reduced in size for cryogenic cooling system, low-resistance signal pathways, and reliability over cryogenic temperature ranges. 2.5D cryogenic integration approach reduces superconducting computing hardware to a small enough size to fit in a cryogenic chamber. In this publication, we demonstrated the assembly of 2.5D packaging integrating using a 100 um thick superconducting interposer with a qubit chip attached on top and a passive chip on the bottom. Interposer's peripheral is then, die attached and Aluminum (AI) wire bond onto the LTCC substrate
Quantum computers perform calculations using quantum bits, or qubits, which can be made from superconducting circuits. These superconducting qubits allow direct control over device parameters while leveraging conventional Si-based fabrication techniques. MIT Lincoln Laboratory is designing and building high performance superconducting qubit devices with increased connectivity and addressability by utilizing advanced process techniques and 3D integration. Our three-tier stack architecture combines separately fabricated qubit, interposer, and routing chips with indium bump bonding. This stack contains high performance qubits, resonators, and couplers, superconducting air bridge crossovers, hard-stop spacing control, superconducting high aspect-ratio through-Si vias, and planarized superconducting routing layers. I will discuss our most recent accomplishments in the fabrication of three-tier stack devices and the effects of additional processing on the uniformity and integrity of their individual components.
Computational ecosystems in which classical supercomputers and general-purpose quantum computers provide a steady increase in value-creating computation capabilities have shown immense progress in recent years. Superconducting qubit technology, in particular, has emerged as a leading candidate for realizing a scalable quantum computing platform ready for paving the way to commercial quantum advantage. However, current academic approaches in fabrication and testing of quantum devices are not scalable and have already started to limit the rapid development of the field. Novel solutions are required to tackle the combined challenge of increasing the qubit count on a quantum processor and the need to further reduce the qubit’s error rates. This, in turn, will lead to a renewed acceleration in qubit manufacturing, test and diagnostics. Here we present aspects of how to move superconducting qubit manufacturing and testing from small-scale laboratory to large-scale fabrication facility environments. To enable this transfer, two key ingredients are demonstrated: (i) A foundry-compatible fabrication process of superconducting qubits that can benefit from the advanced process control in industry-scale CMOS fabrication facilities, and (ii) an acceleration of testing and cryogenic measurement throughput by using a milli-Kelvin cryo-CMOS signal multiplexer operating in near proximity to quantum devices and integrated qubit diagnostic and benchmarking tools with end-to-end data analytics. Although some of these elements have been explored independently, co-development is crucial to enable an efficient scalable development cycle for quantum computing technology. A full development cycle consisting of scalable manufacturing, testing, and benchmarking will enable the large-scale fabrication and control of quantum computing devices and thus pave the way to commercial quantum advantage.
As a key approach to augment Moores Law scaling, 3D integration technologies have enabled small form factor, low cost, diverse, modular and flexible assembly of integrated circuits in the semiconductor industry. It is therefore essential to adopt these technologies to the quantum computing devices which are at the nascent stage and generally require large scale integration to be particle. In this review, we focus on four popular quantum bit (qubit) candidates (trapped ion, superconducting circuit, silicon spin and photon) which are encoded by distinct physical systems but all intrinsically compatible with advanced CMOS fabrication process. We introduce the specific scalability bottlenecks of each qubit type and present the current solutions using 3D integration technologies. We evaluate and classify these technologies into three main categories based on the hierarchy. A brief discussion regarding to the thermal management is also provided. We believe this review serves to provide some useful insights on the contributions of interconnect, integration and packaging to the field of quantum computing where rapid development is ongoing.