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Advanced Etch Technology and Process Integration for Nanopatterning

3D integration and process effects in superconducting qubit devices

Bethany M. Niedzielski

Published Feb 19, 2021• 0 citations
Publisher

Abstract

Quantum computers perform calculations using quantum bits, or qubits, which can be made from superconducting circuits. These superconducting qubits allow direct control over device parameters while leveraging conventional Si-based fabrication techniques. MIT Lincoln Laboratory is designing and building high performance superconducting qubit devices with increased connectivity and addressability by utilizing advanced process techniques and 3D integration. Our three-tier stack architecture combines separately fabricated qubit, interposer, and routing chips with indium bump bonding. This stack contains high performance qubits, resonators, and couplers, superconducting air bridge crossovers, hard-stop spacing control, superconducting high aspect-ratio through-Si vias, and planarized superconducting routing layers. I will discuss our most recent accomplishments in the fabrication of three-tier stack devices and the effects of additional processing on the uniformity and integrity of their individual components.

DOI
10.1117/12.2583734

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Quantum computers perform calculations using quantum bits, or qubits, which can be made from superconducting circuits. These superconducting qubits allow direct control over device parameters while leveraging conventional Si-based fabrication techniques. MIT Lincoln Laboratory is designing and building high performance superconducting qubit devices with increased connectivity and addressability by utilizing advanced process techniques and 3D integration. Our three-tier stack architecture combines separately fabricated qubit, interposer, and routing chips with indium bump bonding. This stack contains high performance qubits, resonators, and couplers, superconducting air bridge crossovers, hard-stop spacing control, superconducting high aspect-ratio through-Si vias, and planarized superconducting routing layers. I will discuss our most recent accomplishments in the fabrication of three-tier stack devices and the effects of additional processing on the uniformity and integrity of their individual components.
As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo> 40 μs) in the presence of silicon posts as near as 350 μm to the qubit.
In this article, we present a technology development of a superconducting qubit device 3D-integrated by flip-chip-bonding and processed following CMOS fabrication standards and contamination rules on 200 mm wafers. We present the utilized proof-of-concept chip designs for qubit- and carrier chip, as well as the respective front-end and back-end fabrication techniques. In characterization of the newly developed microbump technology based on metallized KOH-etched Si-islands, we observe a superconducting transition of the used metal stacks and radio frequency (RF) signal transfer through the bump connection with negligible attenuation. In time-domain spectroscopy of the qubits we find high yield qubit excitation with energy relaxation times of up to 15 us.
© 2019 IEEE. As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo > 40 μs) in the presence of silicon posts as near as 350 μm to the qubit.
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
Abstract To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspectives in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al 0.995 Cu 0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.
Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 10610^6106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.