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arXiv:2608.07306

Flip-chip integrated superconducting qubits using electroplated bump bonds

Yen-An Shih, Rebecca Gharibaan, Barka Khan, Dhananjay Joshi, Siddharth Singh, Martijn F. S. Zwanenburg, Eugene Y. Huang, Nataliia Zhurbina, Figen Yilmaz, Lukas Johannes Splitthoff, Srijit Goswami, Christian Kraglund Andersen

quant-phSubmitted Aug 7, 2026• Announced Aug 10, 2026• 0 citations
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Abstract

Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around $10^6$. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.

Comments
11 pages, 8 figures

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Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 10610^6106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.
Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining 20 μm20\,μ\mathrm{m}20μm thick indium bumps on the control chip with 200 nm200\,\mathrm{nm}200nm thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of T1=(159±14) μsT_1=(159\pm14)\,μ\mathrm{s}T1​=(159±14)μs and T2,echo=(294±42) μsT_{\mathrm{2,echo}}=(294\pm42)\,μ\mathrm{s}T2,echo​=(294±42)μs, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to (20±12) μrad(20\pm12)\,μ\mathrm{rad}(20±12)μrad. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.
Significant progress has been made in building large-scale superconducting quantum processors based on flip-chip technology. In this work, we use flip-chip technology to realize a modified transmon qubit, denoted as the “flipmon,” whose large shunt capacitor is replaced by a vacuum-gap parallel plate capacitor. We place one of the qubit pads and a single Josephson junction on the bottom chip and the other pad on the top chip, which is galvanically connected with the junction through an indium bump. The electric field energy participation ratio can arrive at nearly 53% in air when the vacuum-gap is about 5 μm, thus potentially leading to a lower dielectric loss. The coherence times of the flipmons are obtained in the range of 30–60 μs, which are comparable with that of conventional transmons with similar fabrication processes. The electric field simulation indicates that the metal-air interface's energy participation ratio increases significantly and may dominate the flipmon's decoherence. This suggests that more careful surface treatment needs to be considered. No evidence shows that the indium bumps inside the flipmons cause significant decoherence. With well-designed geometry and good surface treatment, the coherence of the flipmons can be further improved.
The majority of qubit chip integration is realized in a two-dimensional (2D) architecture. Whereas 3D architecture enables more advantages like efficient interconnect routing, allowing for more compact qubit coupling geometries, reducing form factor, and increased connectivity beyond nearest-neighbor interactions. Flip-chip (FC) assembly has been demonstrated to enable 3D architecture connecting qubit chip, interposer, and readout in a sandwich-like structure. Moreover, 3D integration allows the fabrication of hosting chip circuitry without degrading the qubit performance [1]–[4]. Different material considerations have to be taken into account since qubit operational frequency is in the gigahertz range and operating temperature is in the mK range to avoid thermal excitation. Materials that possess superconducting characteristics like Indium (In), Titanium Nitride (TiN), Tantalum Nitride (TaN), and Niobium (Nb) have been discussed as potential interconnect between building blocks [3], [5]. The In bumping on Aluminum (Al) redistribution layers require under-bump metallization (UBM) layers thus introducing multiple fabrication steps before the bonding process. An alternative approach would be to use the existing Al surface to electrochemically grow Al bumps and bond the chip using thermosonic bonding (TSB) at below 150°C to form a homogeneous metal-metal interface [6], [7].
In recent years the interest in building quantum computers with superconducting qubits has steadily increased. Indium is one of the chosen interconnect materials for bonding qubit microchips with Josephson junctions to microelectronic resonators because indium is superconducting and ductile. Indium bump bonding is a common technique for hybridizing pixel radiation sensors to readout chips for some time; however, such detectors operate usually at room temperature. The challenge is to transfer this bonding technique to the fabrication of devices that can operate and withstand very low mKtemperatures. This paper summarizes the current challenges for implementing indium bump bonding to stacked superconducting qubit chips with a particular focus on chip parallelism and superconductivity of the interconnects. A high precision of parallelism between bonded qubit and resonator microchips is essential for minimizing signal loss, and superconducting materials such as indium are required for signal transfer. Photolithography or shadow masking techniques are commonly used to deposit severalμ\muμm-thick indium bumps on microchips. This paper outlines initial experiments to verify and optimize the indium bump deposition and flip-chip bonding for superconducting qubit chips. Stacked chip parallelism is evaluated after flip-chip bonding, the tolerance of the parallelism between stacked chips will be determined with an optical scanner, microscope and Scanning Electron Microscopy (SEM). For the superconductivity of interconnects, daisy chain chips are designed, built and flip-chip bonded. The common Under-Bump Metallization (UBM) for the adhesion of indium bumps to pixel pads requires modification with superconductive material and is investigated with resistance measurements that are taken at room temperature with a probe tester and at mK-temperature in a helium dilution refrigerator.
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.
Abstract As quantum computing evolves from the multi‐qubit stage to large multimodularprocessors, addressability and scalability of quantum hardware will require 3D integration and packaging. The advancement of flip‐chip technology is critical to enabling progress in this area. However, various types of coupling, such as capacitive, inductive, and galvanic, still require systematic research into the principles, quantification, and loss mechanisms. In this article, different types of 3D architecture are examined using flip‐chip technology. The and superconducting resonators with qubit circuits are designed in a modular configuration consisting of two silicon substrates. This arrangement allows numerical analysis and systematic experimental investigation of capacitive, inductive, and galvanic coupling mechanisms. The transmission of short control pulses for fast qubit manipulation is demonstrated and the feasibility of quantum state transfer is theoretically explored, highlighting the potential of this approach for scalable quantum processors. Particular focus is also on the fabrication technology of superconducting indium bumps between silicon substrates.