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arXiv:2106.00341 · Applied Physics Letters

Vacuum-gap transmon qubits realized using flip-chip technology

Xuegang Li, Yingshan Zhang, Chuhong Yang, Zhiyuan Li, Junhua Wang, Tang Su, Mo Chen, Yongchao Li, Cheng-Yao Li, Zhenyu Mi, Xuehui Liang, Chenlu Wang, Zhen Yang, Yulong Feng, Kehuan Linghu, Huikai Xu, Jiaxiu Han, Weiyang Liu, Peng Zhao, Teng Ma, Ruixia Wang, Jing-Ning Zhang, Yu Hao Song, Pei Liu, Ziting Wang, Zhaohua Yang, Guangming Xue, Yirong Jin, Haifeng Yu

Published Nov 1, 2021• 32 citations
arXivHTMLPDF

Abstract

Significant progress has been made in building large-scale superconducting quantum processors based on flip-chip technology. In this work, we use flip-chip technology to realize a modified transmon qubit, denoted as the “flipmon,” whose large shunt capacitor is replaced by a vacuum-gap parallel plate capacitor. We place one of the qubit pads and a single Josephson junction on the bottom chip and the other pad on the top chip, which is galvanically connected with the junction through an indium bump. The electric field energy participation ratio can arrive at nearly 53% in air when the vacuum-gap is about 5 μm, thus potentially leading to a lower dielectric loss. The coherence times of the flipmons are obtained in the range of 30–60 μs, which are comparable with that of conventional transmons with similar fabrication processes. The electric field simulation indicates that the metal-air interface's energy participation ratio increases significantly and may dominate the flipmon's decoherence. This suggests that more careful surface treatment needs to be considered. No evidence shows that the indium bumps inside the flipmons cause significant decoherence. With well-designed geometry and good surface treatment, the coherence of the flipmons can be further improved.

DOI
10.1063/5.0068255

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Significant progress has been made in building large-scale superconducting quantum processors based on flip-chip technology. In this work, we use flip-chip technology to realize a modified transmon qubit, denoted as the “flipmon,” whose large shunt capacitor is replaced by a vacuum-gap parallel plate capacitor. We place one of the qubit pads and a single Josephson junction on the bottom chip and the other pad on the top chip, which is galvanically connected with the junction through an indium bump. The electric field energy participation ratio can arrive at nearly 53% in air when the vacuum-gap is about 5 μm, thus potentially leading to a lower dielectric loss. The coherence times of the flipmons are obtained in the range of 30–60 μs, which are comparable with that of conventional transmons with similar fabrication processes. The electric field simulation indicates that the metal-air interface's energy participation ratio increases significantly and may dominate the flipmon's decoherence. This suggests that more careful surface treatment needs to be considered. No evidence shows that the indium bumps inside the flipmons cause significant decoherence. With well-designed geometry and good surface treatment, the coherence of the flipmons can be further improved.
Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 10610^6106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.
State-of-the-art transmon qubits rely on large capacitors, which systematically improve their coherence due to reduced surface-loss participation. However, this approach increases both the footprint and the parasitic cross-coupling and is ultimately limited by radiation losses---a potential roadblock for scaling up quantum processors to millions of qubits. In this work we present transmon qubits with sizes as low as $36\phantom{\rule{0.2em}{0ex}}\ifmmode\times\else\texttimes\fi{}\phantom{\rule{0.2em}{0ex}}39\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{2}$ with $\ensuremath{\gtrsim}100$-nm-wide vacuum-gap capacitors that are micromachined from commercial silicon-on-insulator wafers and shadow evaporated with aluminum. We achieve a vacuum participation ratio up to 99.6% in an in-plane design that is compatible with standard coplanar circuits. Qubit relaxation-time measurements for small gaps with high zero-point electric field variance of up to 22 V/m reveal a double exponential decay indicating comparably strong qubit interaction with long-lived two-level systems. The exceptionally high selectivity of up to 20 dB to the superconductor-vacuum interface allows us to precisely back out the sub-single-photon dielectric loss tangent of aluminum oxide previously exposed to ambient conditions. In terms of future scaling potential, we achieve a ratio of qubit quality factor to a footprint area equal to $20\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{\ensuremath{-}2}$, which is comparable with the highest T1{T}_{1}T1​ devices relying on larger geometries, a value that could improve substantially for lower surface-loss superconductors.
Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining 20 μm20\,μ\mathrm{m}20μm thick indium bumps on the control chip with 200 nm200\,\mathrm{nm}200nm thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of T1=(159±14) μsT_1=(159\pm14)\,μ\mathrm{s}T1​=(159±14)μs and T2,echo=(294±42) μsT_{\mathrm{2,echo}}=(294\pm42)\,μ\mathrm{s}T2,echo​=(294±42)μs, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to (20±12) μrad(20\pm12)\,μ\mathrm{rad}(20±12)μrad. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.
State-of-the-art transmon qubits rely on large capacitors which systematically improves their coherence due to reduced surface loss participation. However, this approach increases both the footprint and the parasitic cross-coupling and is ultimately limited by radiation losses - a potential roadblock for scaling up quantum processors to millions of qubits. In this work we present transmon qubits with sizes as low as 36$ \times 393939 μmmm^2$ with $\gtrsim$100 nm wide vacuum gap capacitors that are micro-machined from commercial silicon-on-insulator wafers and shadow evaporated with aluminum. After the release in HF vapor we achieve a vacuum participation ratio up to 99.6\% in an in-plane design that is compatible with standard coplanar circuits. Qubit relaxation time measurements for small gaps with high vacuum electric fields of up to 22 V/m reveal a double exponential decay indicating comparably strong coupling to long-lived two-level-systems (TLS). The exceptionally high selectivity of $>$20 dB to the superconductor-vacuum surface allows to precisely back out the sub-single-photon dielectric loss tangent of aluminum oxide exposed to ambient conditions. In terms of future scaling potential we achieve a qubit quality factor by footprint area of 20μs−220 μ\mathrm{s}^{-2}20μs−2, which is on par with the highest T1T_1T1​ devices relying on larger geometries and expected to improve substantially for lower loss superconductors like NbTiN, TiN or Ta.
We demonstrate a superconducting transmon qubit in which a Josephson junction has been engineered to act as its own parallel shunt capacitor. This merged-element transmon potentially offers a smaller footprint than conventional transmons. Because it concentrates the electromagnetic energy inside the junction, it reduces the relative electric field participation from other interfaces. By combining micrometer-scale Al\mathrm{Al}Al/AlO\mathrm{Al}\mathrm{O}AlOx{}_{x}x​/Al\mathrm{Al}Al junctions with long oxidations, we produce functional devices with EJ/EC{E}_{J}/{E}_{C}EJ​/EC​ in the low-transmon regime (${E}_{J}/{E}_{C}\ensuremath{\lesssim}30$). Cryogenic III-VVV measurements show a sharp dI/dVdI/dVdI/dV structure with low subgap conduction. Qubit spectroscopy of tunable versions shows a small number of avoided level crossings, suggesting the presence of two-level systems. We observe mean T1{T}_{1}T1​ times typically in the range of $10--90\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$, with some annealed devices exhibiting ${T}_{1}>100\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$ over several hours. The results suggest that energy relaxation in conventional small-junction transmons is not limited by junction loss.
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.