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Advanced Quantum Technologies

Flip‐Chip Integration of the Superconducting Quantum‐Classical Circuits: Coupling Types

Rustam D. Yusupov, Roman S. Tikhonov, Sergey A. Lisitsyn, Ivan A. Nazhestkin, M. M. Khrenov, Irina E. Tarasova, Sergey V. Egorov, M. Zhdanova, Vladimir N Antonov, D. S. Baranov, V. V. Ryazanov, Olga V. Tikhonova, Nataliya Maleeva, N. V. Klenov, Igor I. Soloviev, Dmitry S. Yakovlev

Published Jul 9, 2025• 0 citations
Publisher

Abstract

Abstract As quantum computing evolves from the multi‐qubit stage to large multimodularprocessors, addressability and scalability of quantum hardware will require 3D integration and packaging. The advancement of flip‐chip technology is critical to enabling progress in this area. However, various types of coupling, such as capacitive, inductive, and galvanic, still require systematic research into the principles, quantification, and loss mechanisms. In this article, different types of 3D architecture are examined using flip‐chip technology. The and superconducting resonators with qubit circuits are designed in a modular configuration consisting of two silicon substrates. This arrangement allows numerical analysis and systematic experimental investigation of capacitive, inductive, and galvanic coupling mechanisms. The transmission of short control pulses for fast qubit manipulation is demonstrated and the feasibility of quantum state transfer is theoretically explored, highlighting the potential of this approach for scalable quantum processors. Particular focus is also on the fabrication technology of superconducting indium bumps between silicon substrates.

DOI
10.1002/qute.202500212

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EPJ Quantum Technology•Feb 11, 2026•1 citation
Abstract As quantum computing evolves from the multi‐qubit stage to large multimodularprocessors, addressability and scalability of quantum hardware will require 3D integration and packaging. The advancement of flip‐chip technology is critical to enabling progress in this area. However, various types of coupling, such as capacitive, inductive, and galvanic, still require systematic research into the principles, quantification, and loss mechanisms. In this article, different types of 3D architecture are examined using flip‐chip technology. The and superconducting resonators with qubit circuits are designed in a modular configuration consisting of two silicon substrates. This arrangement allows numerical analysis and systematic experimental investigation of capacitive, inductive, and galvanic coupling mechanisms. The transmission of short control pulses for fast qubit manipulation is demonstrated and the feasibility of quantum state transfer is theoretically explored, highlighting the potential of this approach for scalable quantum processors. Particular focus is also on the fabrication technology of superconducting indium bumps between silicon substrates.
Abstract As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence ( T 1 , T 2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.
Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 10610^6106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.
Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining 20 μm20\,μ\mathrm{m}20μm thick indium bumps on the control chip with 200 nm200\,\mathrm{nm}200nm thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of T1=(159±14) μsT_1=(159\pm14)\,μ\mathrm{s}T1​=(159±14)μs and T2,echo=(294±42) μsT_{\mathrm{2,echo}}=(294\pm42)\,μ\mathrm{s}T2,echo​=(294±42)μs, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to (20±12) μrad(20\pm12)\,μ\mathrm{rad}(20±12)μrad. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.
Flip-chip architectures have recently enabled significant scaling-up of multi-qubit circuits and have been used to assemble hybrid quantum systems that combine different substrates, for example, for quantum acoustics experiments. The standard flip-chip method uses superconducting galvanic connections between two substrates, typically implemented using sophisticated indium wafer-bonding systems, which give highly reliable and temperature-cyclable assemblies, but are expensive, somewhat inflexible in design, and require robust substrates that can sustain the large compressive forces required to cold-weld the indium bonds. A much simpler method is to assemble dies using very low-force contacts and air-dried adhesives, although this does not provide a galvanic contact between the dies. Here, we demonstrate that the latter technique can be used to reliably couple superconducting qubit circuits, in which the qubits are on separate dies, without the need for a galvanic connection. We demonstrate full vector qubit control of each qubit on each of the two dies, with high-fidelity single-shot readout, and further demonstrate entanglement-generating excitation swaps as well as benchmark a controlled-Z entangling gate between the two qubits on the two dies. This exemplifies a simple and inexpensive assembly method for two-plus-one-dimensional quantum circuit integration that supports the use of delicate or unusually shaped substrates.
Abstract Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of 9×10−39 \times 10^{-3}9×10−3 9 × 10 − 3 in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of 6×10−46 \times 10^{-4}6×10−4 6 × 10 − 4 , consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of 7×10−37 \times 10^{-3}7×10−3 7 × 10 − 3 extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.