Solid-state qubits integrated with superconducting through-silicon vias
D. Yost, Mollie E. Schwartz, Justin Mallek, Danna Rosenberg, Corey Stull, Jonilyn Yoder, Greg Calusine, Matthew Cook, Rabindra Nath Das, Alexandra L. Day, Evan B. Golden, David K. Kim, Alexander J. Melville, Bethany M. Niedzielski, Wayne H. Woods, Andrew J. Kerman, William D. Oliver
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μm wide by 20 μm long by 200 μm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
The development of superconducting quantum computing has seen a rapid acceleration in recent years. The number of controllable qubits fabricated on-chip has steadily increased in the pursuit of more computational power. 3D integration has become a key enabling technology for the scalability of these larger systems due to the architectural flexibility it offers, mirroring its impact on conventional electronics. As part of this development, superconducting throughsilicon vias (TSVs) have recently emerged as a method of breaking the wiring plane and routing signals through the substrate as well as for other, more novel, applications such as acting as the capacitive component of a new type of superconducting qubit. This thesis will discuss the simulation, fabrication and measurement of superconducting TSVs. Using ANSYS HFSS electromagnetic simulation software, the geometric parameters of TSV-integrated co-planar waveguides were optimised for the transmission of microwave signals. In addition, a TSV-integrated tunable qubit coupler was simulated and the effect of the device’s geometry on the various capacitances within the device, and in turn on the device’s parameters, such as the charging and Josephson energies, was investigated. As a leading cause of signal degradation in electronic devices, crosstalk should be removed from devices as far as possible. Varying the number and arrangement of grounding TSVs was explored as a strategy for the mitigation of crosstalk between adjacent TSVs and it was found that using 4 ground TSVs to shield the signal TSV resulted in a dramatic reduction in crosstalk, with values of S41 <−140dB at 4GHz. For the fabricated samples, a comparison was made of different Bosch etches used to define the TSVs and it was determined that the ICP power and total etch time were highly influential in the degree of sidewall roughness. Methods of sidewall smoothing were also investigated, with KOH wet etching found to offer near atomic-level smoothness. Finally, the fabricated samples were characterised using, among other methods, cryogenic spectroscopy. A novel application of the method of calibrated cryogenic S-parameter measurement to superconducting TSVs is also presented, with the TSV-integrated co-planar waveguide structure under test exhibiting a peak transmission of -1.44dB.
As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo> 40 μs) in the presence of silicon posts as near as 350 μm to the qubit.
We propose superconducting-semiconducting (super-semi) qubit and coupler designs based on high-quality compact through-silicon vias (TSVs) to overcome challenges introduced by materials and processing required to fabricate high-quality super-semi Josephson junctions. In our designs, an interposer ``probe'' wafer containing TSVs is used to contact a sample wafer with, e.g., a superconductor-proximitized epitaxially grown germanium quantum well. By utilizing the capacitance of the probe-wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions in the semiconducting wafer, such as the graded buffer layers sometimes required for epitaxial growth. Through simulations, we find that the probe wafer can reduce the electric field participation of the qubit in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial-layer thickness approaches $100\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{m}$. We also show how the qubit-coherence improvements achieved via this scheme are extensible to multiqubit systems that have tunable qubit-qubit couplings without magnetic fields. This approach additionally shrinks the on-chip footprint of voltage-tunable superconducting qubits while homogenizing critical wiring structures independent of semiconducting materials, which could aid in accelerating the understanding of super-semi heterostructures in a variety of systems.
Abstract To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspectives in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al 0.995 Cu 0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.