We propose superconducting-semiconducting (super-semi) qubit and coupler designs based on high-quality compact through-silicon vias (TSVs) to overcome challenges introduced by materials and processing required to fabricate high-quality super-semi Josephson junctions. In our designs, an interposer ``probe'' wafer containing TSVs is used to contact a sample wafer with, e.g., a superconductor-proximitized epitaxially grown germanium quantum well. By utilizing the capacitance of the probe-wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions in the semiconducting wafer, such as the graded buffer layers sometimes required for epitaxial growth. Through simulations, we find that the probe wafer can reduce the electric field participation of the qubit in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial-layer thickness approaches $100\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{m}$. We also show how the qubit-coherence improvements achieved via this scheme are extensible to multiqubit systems that have tunable qubit-qubit couplings without magnetic fields. This approach additionally shrinks the on-chip footprint of voltage-tunable superconducting qubits while homogenizing critical wiring structures independent of semiconducting materials, which could aid in accelerating the understanding of super-semi heterostructures in a variety of systems.
We propose superconducting-semiconducting (super-semi) qubit and coupler designs based on high-quality compact through-silicon vias (TSVs) to overcome challenges introduced by materials and processing required to fabricate high-quality super-semi Josephson junctions. In our designs, an interposer ``probe'' wafer containing TSVs is used to contact a sample wafer with, e.g., a superconductor-proximitized epitaxially grown germanium quantum well. By utilizing the capacitance of the probe-wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions in the semiconducting wafer, such as the graded buffer layers sometimes required for epitaxial growth. Through simulations, we find that the probe wafer can reduce the electric field participation of the qubit in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial-layer thickness approaches 100\ensuremathμm. We also show how the qubit-coherence improvements achieved via this scheme are extensible to multiqubit systems that have tunable qubit-qubit couplings without magnetic fields. This approach additionally shrinks the on-chip footprint of voltage-tunable superconducting qubits while homogenizing critical wiring structures independent of semiconducting materials, which could aid in accelerating the understanding of super-semi heterostructures in a variety of systems.
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μm wide by 20 μm long by 200 μm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
The development of superconducting quantum computing has seen a rapid acceleration in recent years. The number of controllable qubits fabricated on-chip has steadily increased in the pursuit of more computational power. 3D integration has become a key enabling technology for the scalability of these larger systems due to the architectural flexibility it offers, mirroring its impact on conventional electronics. As part of this development, superconducting throughsilicon vias (TSVs) have recently emerged as a method of breaking the wiring plane and routing signals through the substrate as well as for other, more novel, applications such as acting as the capacitive component of a new type of superconducting qubit. This thesis will discuss the simulation, fabrication and measurement of superconducting TSVs. Using ANSYS HFSS electromagnetic simulation software, the geometric parameters of TSV-integrated co-planar waveguides were optimised for the transmission of microwave signals. In addition, a TSV-integrated tunable qubit coupler was simulated and the effect of the device’s geometry on the various capacitances within the device, and in turn on the device’s parameters, such as the charging and Josephson energies, was investigated. As a leading cause of signal degradation in electronic devices, crosstalk should be removed from devices as far as possible. Varying the number and arrangement of grounding TSVs was explored as a strategy for the mitigation of crosstalk between adjacent TSVs and it was found that using 4 ground TSVs to shield the signal TSV resulted in a dramatic reduction in crosstalk, with values of S41 <−140dB at 4GHz. For the fabricated samples, a comparison was made of different Bosch etches used to define the TSVs and it was determined that the ICP power and total etch time were highly influential in the degree of sidewall roughness. Methods of sidewall smoothing were also investigated, with KOH wet etching found to offer near atomic-level smoothness. Finally, the fabricated samples were characterised using, among other methods, cryogenic spectroscopy. A novel application of the method of calibrated cryogenic S-parameter measurement to superconducting TSVs is also presented, with the TSV-integrated co-planar waveguide structure under test exhibiting a peak transmission of -1.44dB.
Voltage-tunable Josephson junctions (VT-JJs) are an emerging element in superconducting quantum electronics with potential to expand the functionality of conventional designs. While VT-JJs are largely compatible with wafer-scale semiconductor processing, their integration into quantum circuits remains a challenge due to unmitigated semiconductor microwave loss. Here, a deep mesa etch process, wherein the epitaxial material is removed except the VT-JJ device, will facilitate the integration of VT-JJs with low-microwave-loss circuit elements by allowing these circuit elements to be placed directly on a low-loss substrate. A Germanium quantum well is grown by Molecular Beam Epitaxy (MBE) on a float zone silicon substrate with in-situ deposited aluminum contacts. This combination allows the formation of an oxide-free superconductor-semiconductor interface. The deep mesa etch process is optimized to produce a sidewall taper sufficient for continuous metal deposition from the substrate to the top of the mesa for electrostatic gate electrodes and interconnects. The fabricated Josephson junctions demonstrate gate-tunable supercurrents with a maximum critical current over 100 nA and critical-current normal-resistance product of 8.63μV. These results demonstrate a pathway toward improved integration of voltage-tunable superconducting circuit elements with quantum electronic building blocks such as couplers and qubits.
Superconducting qubit based on superconducting circuits consist of a superconducting capacitor and a Josephson junction with the transmon geometry is extensively used in advanced quantum processors, pursuing scalable quantum computing. The tuning of the qubit frequency of the transmon relies on magnetic flux-dependent interference between the supercurrents of two superconductor-insulator-superconductor (S-I-S) Josephson junctions in a superconducting loop. Josephson junction based on superconductor-semiconductor-superconductor (S-Sm-S) materials opens up a possibility to the gate-tunable transmon, referred to as the "gatemon", in which the qubit frequency can be tuned by electrostatic mean. Recent realizations of gatemons on III-V material platforms show impressive development on the alternative to the transmon, yet still leave a big question on the scalability. The silicon-germanium (SiGe) heterostructure is one of the potential platforms to host hybrid devices due to its high hole mobility and the low Schottky barrier at the Ge-metal interface. Additionally, the compatibility with the silicon-based semiconductor industry is a capable advantage for the scaling-up qubit platform.In this thesis, we develop gatemons based on the Al-Ge-Al Josephson junction in the SiGe heterostructure. Firstly, the robust fabrication recipe, found on a top-down approach, for Josephson Field Effect Transistors (JoFETs) is established. We perform measurements exhaustively on the JoFETs to study their properties as a function of the gate voltage, temperature, and magnetic field. The devices show gate-tunability of the critical current and the normal state resistance . The devices are estimated to have a high-transparency superconductor-semiconductor interface, as demonstrated by the high product on the SiGe heterostructure. In the finite-voltage regime, the features corresponded to multiple Andreev reflections (MARs) are observed. Then, we fabricate and characterize niobium nitride (NbN) superconducting resonators on SiGe heterostructure. We measure the resonators in the transmission mode and extract the resonant frequency , internal quality factor, and coupling quality factor from the transmission coefficient. Following that, we develop the fabrication process to integrate Al-Ge-Al junctions shunted with capacitors, or, in other words, gatemon, into the resonator scheme and perform the fabrication according to the design. We demonstrate the anticrossing feature in one of the fabricated gatemons. The resonant frequency of the gatemon is mapped using the two-tone spectroscopy technique and is found to be gate-tunable. The qubit has large spectral linewidth, implying a low coherence time. Additionally, we conduct the current-phase relationship (CPR) measurement on the junctions in the Superconducting QUantum Interference Device (SQUID) geometry. We can demonstrate that the junctions pose non-sinusoidal CPR. Further, the integer and half-integer Shapiro steps are observed in the current-voltage characteristic curves of irradiated junctions. This indicates that our junctions have the element, which can open up another possibility toward protected qubits.
The large physical size of superconducting qubits and their associated on-chip control structures presents a practical challenge toward building a large-scale quantum computer. In particular, transmons require a high-quality-factor shunting capacitance that is typically achieved by using a large coplanar capacitor. Other components, such as superconducting microwave resonators used for qubit state readout, are typically constructed from coplanar waveguides, which are millimeters in length. Here, we use compact superconducting through-silicon vias to realize lumped-element capacitors in both qubits and readout resonators to significantly reduce the on-chip footprint of both of these circuit elements. We measure two types of devices to show that through-silicon vias are of sufficient quality to be used as capacitive circuit elements and provide a significant reduction in size over existing approaches.