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IEEE Electronics Packaging Technology Conference (EPTC)

2.5D Cryogenic Packaging for Advanced Quantum Processors

Norhanani Binte Jaafar, Li Hongyu, Ya-Ching Tseng, Yong Chyn Ng, Daniel Lau

Published Dec 2, 2025• 0 citations
Publisher

Abstract

2.5D packaging improves performance and power efficiency due to shorter connectivity distance, enhances signal integrity owing to reduce wiring lengths and higher integration densities. Current technologies cannot provide an integration technique that can handle thousands of single flux quantum devices required for operation. Other criteria include high integration density per chip, a reduced in size for cryogenic cooling system, low-resistance signal pathways, and reliability over cryogenic temperature ranges. 2.5D cryogenic integration approach reduces superconducting computing hardware to a small enough size to fit in a cryogenic chamber. In this publication, we demonstrated the assembly of 2.5D packaging integrating using a 100 um thick superconducting interposer with a qubit chip attached on top and a passive chip on the bottom. Interposer's peripheral is then, die attached and Aluminum (AI) wire bond onto the LTCC substrate

DOI
10.1109/eptc67330.2025.11392196

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2.5D packaging improves performance and power efficiency due to shorter connectivity distance, enhances signal integrity owing to reduce wiring lengths and higher integration densities. Current technologies cannot provide an integration technique that can handle thousands of single flux quantum devices required for operation. Other criteria include high integration density per chip, a reduced in size for cryogenic cooling system, low-resistance signal pathways, and reliability over cryogenic temperature ranges. 2.5D cryogenic integration approach reduces superconducting computing hardware to a small enough size to fit in a cryogenic chamber. In this publication, we demonstrated the assembly of 2.5D packaging integrating using a 100 um thick superconducting interposer with a qubit chip attached on top and a passive chip on the bottom. Interposer's peripheral is then, die attached and Aluminum (AI) wire bond onto the LTCC substrate
An advanced quantum processor requires millions of qubits but is at present limited in scalability due to limitations in the wiring of qubits. A 2.5D silicon (Si) interposer provides an attractive solution in enabling the scalability of the qubit devices. However, some qubits, like the superconducting qubits and solid-state spin-orbit qubits, operate in cryogenic temperatures below 1K. Copper (Cu) interconnects in conventional Si interposers are not superconductive in nature. As such, these metals contribute to losses and result in resistive heating, which can undesirably increase the temperature of the qubits during operation. This paper reports the full demonstration and electrical characterization of a cryogenic interposer with superconducting interconnects and TSV, using CMOS compatible materials like Aluminium (Al), Titanium (Ti), Titanium Nitride (TiN) and Tantalum (Ta).
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.
Current superconducting quantum computers (QC) rely on a brute-force scaling approach where quantum chips operating at the millikelvin stage inside dilution refrigerators are connected to room-temperature electronics via an ever-increasing number of signal wires. In order to drastically scale up such systems without facing refrigeration challenges, these quantum interface electronics need to be integrated at cryogenic temperatures, ideally at the same stage as qubits. In this paper, we show that, by employing energy-efficient digital superconducting microchips based on single flux quantum (SFQ) technology, all essential functions to operate a full stack quantum computer can be integrated at 10 mK. They include digital qubit charge control and magnetic flux control for single- and two-qubit gates, as well as digital qubit readout.
Large-scale quantum computers with more than 10510^5105 qubits will likely be built within the next decade. Trapped ions, semiconductor devices, and superconducting qubits among other physical implementations are still confined in the realm of medium-scale quantum integration (∼100\sim 100∼100 qubits); however, they show promise toward large-scale quantum integration. Building large-scale quantum processing units will require truly scalable control and measurement classical coprocessors as well as suitable wiring methods. In this blue paper, we introduce a fully vertical interconnect that will make it possible to address ∼105\sim 10^5∼105 superconducting qubits fabricated on a single silicon or sapphire chip: Pin-chip bonding. This method permits signal transmission from DC to ∼10\sim 10∼10 GHz, both at room temperature and at cryogenic temperatures down to ∼10\sim 10∼10 mK. At temperatures below ∼1\sim 1∼1 K, the on-chip wiring contact resistance is close to zero and all signal lines are in the superconducting state. High-density wiring is achieved by means of a fully vertical interconnect that interfaces the qubit array with a network of rectangular coaxial ribbon cables. Pin-chip bonding is fully compatible with classical high-density test board applications as well as with other qubit implementations.
This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.