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IEEE Electronic Components and Technology Conference (ECTC)

Demonstration of a CMOS-Compatible Superconducting Cryogenic Interposer for Advanced Quantum Processors

King-Jien Chui, Hongyu Li, Yong Chyn Ng, Chit Siong Lau, Kuan Eng Johnson Goh, D. J. Huang, Ya-Ching Tseng, Jhewn-Kuang Chen, Hao Yu, Norhanani Binte Jaafar, Haifeng Lin, Binni Varghese

Published May 1, 2023• 13 citations
Publisher

Abstract

An advanced quantum processor requires millions of qubits but is at present limited in scalability due to limitations in the wiring of qubits. A 2.5D silicon (Si) interposer provides an attractive solution in enabling the scalability of the qubit devices. However, some qubits, like the superconducting qubits and solid-state spin-orbit qubits, operate in cryogenic temperatures below 1K. Copper (Cu) interconnects in conventional Si interposers are not superconductive in nature. As such, these metals contribute to losses and result in resistive heating, which can undesirably increase the temperature of the qubits during operation. This paper reports the full demonstration and electrical characterization of a cryogenic interposer with superconducting interconnects and TSV, using CMOS compatible materials like Aluminium (Al), Titanium (Ti), Titanium Nitride (TiN) and Tantalum (Ta).

DOI
10.1109/ectc51909.2023.00109

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An advanced quantum processor requires millions of qubits but is at present limited in scalability due to limitations in the wiring of qubits. A 2.5D silicon (Si) interposer provides an attractive solution in enabling the scalability of the qubit devices. However, some qubits, like the superconducting qubits and solid-state spin-orbit qubits, operate in cryogenic temperatures below 1K. Copper (Cu) interconnects in conventional Si interposers are not superconductive in nature. As such, these metals contribute to losses and result in resistive heating, which can undesirably increase the temperature of the qubits during operation. This paper reports the full demonstration and electrical characterization of a cryogenic interposer with superconducting interconnects and TSV, using CMOS compatible materials like Aluminium (Al), Titanium (Ti), Titanium Nitride (TiN) and Tantalum (Ta).
Abstract The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
2.5D packaging improves performance and power efficiency due to shorter connectivity distance, enhances signal integrity owing to reduce wiring lengths and higher integration densities. Current technologies cannot provide an integration technique that can handle thousands of single flux quantum devices required for operation. Other criteria include high integration density per chip, a reduced in size for cryogenic cooling system, low-resistance signal pathways, and reliability over cryogenic temperature ranges. 2.5D cryogenic integration approach reduces superconducting computing hardware to a small enough size to fit in a cryogenic chamber. In this publication, we demonstrated the assembly of 2.5D packaging integrating using a 100 um thick superconducting interposer with a qubit chip attached on top and a passive chip on the bottom. Interposer's peripheral is then, die attached and Aluminum (AI) wire bond onto the LTCC substrate
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μμμm wide by 20 μμμm long by 200 μμμm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
Quantum computing holds the promise to solve problems that are currently intractable by classical computing platforms. Such computing framework relies on the properties of quantum bits (qubits) that operates at cryogenic temperatures well below 1K. Besides a quantum processor, an operational quantum computer needs a classical electronic controller reading out the electrical signals generated by the qubits and the providing electrical control to perform the required operations on the qubits. Since today’s quantum processors comprise a low number of qubits (<10), most controlling electronics can operate at room temperature and be connected by bulky interconnects to the cryogenic qubit chamber. However, when scaling up to the thousands of qubits required in a practical quantum algorithm, the classical electronics must be placed at cryogenic temperature to simplify the interconnects and allow a compact, reliable and scalable system. In this work, we propose the fully-integrated implementation in standard CMOS technology of the electronic read-out for spin qubits. Simulations show that the proposed current read-out circuit can achieve a 10MHz bandwidth that is 10X wider than current state-of-the-art read-outs while keeping comparable noise performance and operating at 4.2K. Such results are a promising indication that cryogenic CMOS circuits can provide the building blocks for the integration of the classical electronic controller for future scalable quantum computers.