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arXiv:1810.08580

High-Density Qubit Wiring: Pin-Chip Bonding for Fully Vertical Interconnects

M. Mariantoni, A.V. Bardysheva

Published Oct 19, 2018• 3 citations
arXivHTMLPDF

Abstract

Large-scale quantum computers with more than $10^5$ qubits will likely be built within the next decade. Trapped ions, semiconductor devices, and superconducting qubits among other physical implementations are still confined in the realm of medium-scale quantum integration ($\sim 100$ qubits); however, they show promise toward large-scale quantum integration. Building large-scale quantum processing units will require truly scalable control and measurement classical coprocessors as well as suitable wiring methods. In this blue paper, we introduce a fully vertical interconnect that will make it possible to address $\sim 10^5$ superconducting qubits fabricated on a single silicon or sapphire chip: Pin-chip bonding. This method permits signal transmission from DC to $\sim 10$ GHz, both at room temperature and at cryogenic temperatures down to $\sim 10$ mK. At temperatures below $\sim 1$ K, the on-chip wiring contact resistance is close to zero and all signal lines are in the superconducting state. High-density wiring is achieved by means of a fully vertical interconnect that interfaces the qubit array with a network of rectangular coaxial ribbon cables. Pin-chip bonding is fully compatible with classical high-density test board applications as well as with other qubit implementations.

DOI
10.48550/arxiv.1810.08580

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Large-scale quantum computers with more than 10510^5105 qubits will likely be built within the next decade. Trapped ions, semiconductor devices, and superconducting qubits among other physical implementations are still confined in the realm of medium-scale quantum integration (∼100\sim 100∼100 qubits); however, they show promise toward large-scale quantum integration. Building large-scale quantum processing units will require truly scalable control and measurement classical coprocessors as well as suitable wiring methods. In this blue paper, we introduce a fully vertical interconnect that will make it possible to address ∼105\sim 10^5∼105 superconducting qubits fabricated on a single silicon or sapphire chip: Pin-chip bonding. This method permits signal transmission from DC to ∼10\sim 10∼10 GHz, both at room temperature and at cryogenic temperatures down to ∼10\sim 10∼10 mK. At temperatures below ∼1\sim 1∼1 K, the on-chip wiring contact resistance is close to zero and all signal lines are in the superconducting state. High-density wiring is achieved by means of a fully vertical interconnect that interfaces the qubit array with a network of rectangular coaxial ribbon cables. Pin-chip bonding is fully compatible with classical high-density test board applications as well as with other qubit implementations.
Scaling superconducting quantum processors to hundreds of qubits is essential for demonstrating quantum advantage and implementing quantum error correction codes with larger distances. A key challenge is integrating control and readout wiring without compromising cryogenic or electronic performance. To address this, we performed a systematic analysis of the thermal budget within a dilution refrigerator and developed high-density 0.5 mm SCuNi-CuNi coaxial cable sets optimized for heat load management. This enables the integration of 696 control lines and 40 readout amplification chains into a dilution refrigerator with a cooling power of 1 mW at 100 mK, maintaining a stable base temperature of ∼8 mK for over a year. We validated the platform's performance with two large-scale quantum processors: a 540-qubit processor with an average T1 of 35 μs and a 156-qubit processor with 182 tunable couplers, achieving average fidelities of 99.9% for single-qubit gates and 99.0% for two-qubit gates. This study demonstrates a viable high-density wiring solution for controlling and measuring processors at the 500-qubit scale and provides critical engineering insights for larger-scale quantum computing systems.
Quantum computing architectures with ten or more quantum bits (qubits) have been implemented using trapped ions and superconducting devices. The next milestone in the quest for a quantum computer is the realization of quantum error correction codes. Such codes will require a large number of qubits that must be controlled and measured by means of classical electronics. This scaling up leads to a number of problems and sources of error that must be accounted for in order to have an operational system. \n \nOne architectural aspect requiring immediate attention is the realization of a suitable interconnect between the quantum and classical hardware. Our proposed solution to this wiring problem is the quantum socket, a three-dimensional wiring method for qubits with superior performance as compared to two-dimensional methods based on wire bonding. The quantum socket also provides a means to counteract another scaling problem, the coupling of qubits to unwanted cavity modes resulting in coherent leakage error. By following our proposed wiring methodologies, half-wave fencing or antinode pinning, we show how the error due to leakage can be mitigated to orders of magnitude below current state-of-the-art error probabilities.
3-D chip integration is considered to be the best way for further increasing the number of qubits on chip, and also for integration of qubits and readout electronics. Works have been done to stack two wafers with superconductive interconnections as a demonstration for feasibility of 3-D qubit integration.But all of them use an extra layer of adhesives, indium in particular, to join two neighboring planes.Indium is a good choice of adhesive for wafer bonding at cryogenic temperature. However, there are potential issues to employ this extra layer of adhesive. First, the critical temperature (Tc) of indium being 3.4K means it is suitable preferably for superconducting qubits, but not good enough for qubit implementations or other cryogenic that have above-4K expectations. Second, one general problem in wafer bonding is that alignment is not accurate. Adding an extra layer of anything increases the degree of misalignment. In this work, the extra adhesive layer is abandoned and two wafers are bonded by direct-bonding technique. First, niobium nitride (NbN) is chosen to be the skeleton for this 3-D structure due to its high Tc (18K) as well as its simple composition hence easy fabrication. Sputtering is the method used to fabricate such metal nitride. Sample with Tc=15.6K has been measured so far. Second, both wafer-scale and miniaturized pattern are designed to measure contact resistance of direct bonding of NbN films in room and cryogenic temperature. This work shows the potential of direct-wafer bonding in 3-D chip integration at cryogenic environment, and could further lead to scaling up of quantum processors.
To create a practical quantum computer, one must produce and incorporate around one million qubits. The greatest hurdle lies in finding a technology that allows for precise control over two-level quantum systems while enabling mass production. While achieving a high quantity of qubits is crucial, the most critical factor is qubit quality, which is measured by the number of gate operations a qubit can perform during its coherence time (also known as its lifetime). Unfortunately, qubits are susceptible to environmental disturbances, leading to the degradation of their quantum states over time. To sustain the computation process, a minimum threshold for quantum error correction is required, which is approximately 1000 times the qubit time. While researchers have managed to develop high-quality qubits, they have encountered limitations in terms of number of qubits. The methodology to address this challenge is through scalability using 2D technology at the expense of larger chip sizes, increased complexity, and subsequently, a potential compromise in qubit quality. Hence, to overcome this issue we have to look for vertical interconnects for large-scale qubit integration. Interconnects are not new they have already been used in the semiconductor industry. However, superconducting qubit is only facilitated at cryogenic temperature hence the materials that are traditionally used for electrical conductivity, like Cu and tungsten (w) are not superconducting in nature. Therefore, in this paper, we have analyzed the vertical superconducting interconnects filled with different superconducting materials using the time-dependent Ginzburg-landau equation and observed how the temperature-dependent London penetration depth results in an increase in cooper pair density or superconducting electron density.
Quantum chips form the foundational hardware for quantum computing, promising transformative impacts across optimization, secure communications, and artificial intelligence. This paper surveys five leading qubit implementations—superconducting circuits, neutral-atom arrays, trapped ions, photonic systems, and silicon-based quantum dots—highlighting their distinct operating principles, recent milestones, and inherent trade-offs. Superconducting platforms leverage mature microfabrication to achieve hundreds to thousands of qubits with rapid gate times but require millikelvin environments and face millisecond-scale coherence limits. Neutral-atom and ion-trap architectures offer exceptionally long coherence (seconds to hours) and high-fidelity operations, making them ideal for quantum memory and precision simulation, yet scaling remains constrained by control complexity. Photonic chips excel at room-temperature operation and quantum networking via entangled photons, though deterministic two-qubit gates and on-chip integration pose challenges. Silicon quantum dots promise CMOS compatibility and sub-microsecond spin coherence, but demand atomic-scale fabrication precision and advanced cryogenic control. We analyze the tension between qubit count, error rates, and engineering practicality, and discuss emerging solutions such as hybrid integration, advanced error-correction codes, and novel materials. Looking ahead, coordinated optimization across these platforms—combining fast superconducting processors, long-lived atomic memories, photonic interconnects, and scalable silicon arrays—will be critical to transition quantum chips from research prototypes to industrially viable systems that redefine computing, communications, and AI.
In recent years the interest in building quantum computers with superconducting qubits has steadily increased. Indium is one of the chosen interconnect materials for bonding qubit microchips with Josephson junctions to microelectronic resonators because indium is superconducting and ductile. Indium bump bonding is a common technique for hybridizing pixel radiation sensors to readout chips for some time; however, such detectors operate usually at room temperature. The challenge is to transfer this bonding technique to the fabrication of devices that can operate and withstand very low mKtemperatures. This paper summarizes the current challenges for implementing indium bump bonding to stacked superconducting qubit chips with a particular focus on chip parallelism and superconductivity of the interconnects. A high precision of parallelism between bonded qubit and resonator microchips is essential for minimizing signal loss, and superconducting materials such as indium are required for signal transfer. Photolithography or shadow masking techniques are commonly used to deposit severalμ\muμm-thick indium bumps on microchips. This paper outlines initial experiments to verify and optimize the indium bump deposition and flip-chip bonding for superconducting qubit chips. Stacked chip parallelism is evaluated after flip-chip bonding, the tolerance of the parallelism between stacked chips will be determined with an optical scanner, microscope and Scanning Electron Microscopy (SEM). For the superconductivity of interconnects, daisy chain chips are designed, built and flip-chip bonded. The common Under-Bump Metallization (UBM) for the adhesion of indium bumps to pixel pads requires modification with superconductive material and is investigated with resistance measurements that are taken at room temperature with a probe tester and at mK-temperature in a helium dilution refrigerator.