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Direct Bonding of NbN for 3-D Chip Integration of quantum processors

Ye Li

Published Jan 1, 2019• 0 citations
OpenAlex

Abstract

3-D chip integration is considered to be the best way for further increasing the number of qubits on chip, and also for integration of qubits and readout electronics. Works have been done to stack two wafers with superconductive interconnections as a demonstration for feasibility of 3-D qubit integration.But all of them use an extra layer of adhesives, indium in particular, to join two neighboring planes.Indium is a good choice of adhesive for wafer bonding at cryogenic temperature. However, there are potential issues to employ this extra layer of adhesive. First, the critical temperature (Tc) of indium being 3.4K means it is suitable preferably for superconducting qubits, but not good enough for qubit implementations or other cryogenic that have above-4K expectations. Second, one general problem in wafer bonding is that alignment is not accurate. Adding an extra layer of anything increases the degree of misalignment. In this work, the extra adhesive layer is abandoned and two wafers are bonded by direct-bonding technique. First, niobium nitride (NbN) is chosen to be the skeleton for this 3-D structure due to its high Tc (18K) as well as its simple composition hence easy fabrication. Sputtering is the method used to fabricate such metal nitride. Sample with Tc=15.6K has been measured so far. Second, both wafer-scale and miniaturized pattern are designed to measure contact resistance of direct bonding of NbN films in room and cryogenic temperature. This work shows the potential of direct-wafer bonding in 3-D chip integration at cryogenic environment, and could further lead to scaling up of quantum processors.

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3-D chip integration is considered to be the best way for further increasing the number of qubits on chip, and also for integration of qubits and readout electronics. Works have been done to stack two wafers with superconductive interconnections as a demonstration for feasibility of 3-D qubit integration.But all of them use an extra layer of adhesives, indium in particular, to join two neighboring planes.Indium is a good choice of adhesive for wafer bonding at cryogenic temperature. However, there are potential issues to employ this extra layer of adhesive. First, the critical temperature (Tc) of indium being 3.4K means it is suitable preferably for superconducting qubits, but not good enough for qubit implementations or other cryogenic that have above-4K expectations. Second, one general problem in wafer bonding is that alignment is not accurate. Adding an extra layer of anything increases the degree of misalignment. In this work, the extra adhesive layer is abandoned and two wafers are bonded by direct-bonding technique. First, niobium nitride (NbN) is chosen to be the skeleton for this 3-D structure due to its high Tc (18K) as well as its simple composition hence easy fabrication. Sputtering is the method used to fabricate such metal nitride. Sample with Tc=15.6K has been measured so far. Second, both wafer-scale and miniaturized pattern are designed to measure contact resistance of direct bonding of NbN films in room and cryogenic temperature. This work shows the potential of direct-wafer bonding in 3-D chip integration at cryogenic environment, and could further lead to scaling up of quantum processors.
In recent years the interest in building quantum computers with superconducting qubits has steadily increased. Indium is one of the chosen interconnect materials for bonding qubit microchips with Josephson junctions to microelectronic resonators because indium is superconducting and ductile. Indium bump bonding is a common technique for hybridizing pixel radiation sensors to readout chips for some time; however, such detectors operate usually at room temperature. The challenge is to transfer this bonding technique to the fabrication of devices that can operate and withstand very low mKtemperatures. This paper summarizes the current challenges for implementing indium bump bonding to stacked superconducting qubit chips with a particular focus on chip parallelism and superconductivity of the interconnects. A high precision of parallelism between bonded qubit and resonator microchips is essential for minimizing signal loss, and superconducting materials such as indium are required for signal transfer. Photolithography or shadow masking techniques are commonly used to deposit severalμ\muμm-thick indium bumps on microchips. This paper outlines initial experiments to verify and optimize the indium bump deposition and flip-chip bonding for superconducting qubit chips. Stacked chip parallelism is evaluated after flip-chip bonding, the tolerance of the parallelism between stacked chips will be determined with an optical scanner, microscope and Scanning Electron Microscopy (SEM). For the superconductivity of interconnects, daisy chain chips are designed, built and flip-chip bonded. The common Under-Bump Metallization (UBM) for the adhesion of indium bumps to pixel pads requires modification with superconductive material and is investigated with resistance measurements that are taken at room temperature with a probe tester and at mK-temperature in a helium dilution refrigerator.
Quantum computing relies on a blend of superposition and entanglement phenomena of qubit devices to solve problems. It promises unparalleled computational throughput that has been earmarked to surpass that of even supercomputers. While the concept of quantum computing and quantum information processing has been established, there have been challenges in the scalability of qubits and the heterogeneous integration of qubits with control, read-out electronics. With the increased number of qubit devices, there is a pressing need to incorporate the many interconnects to address the qubits. 2.5D/3D advanced wafer-level packaging provides a solution to address these needs. Currently, Nb or Nb-based metals is one of the preferred superconducting interconnects for quantum devices and circuitry routing. This paper discusses the demonstration of a room-temperature wafer-to-wafer Nb bonding process for potential 3D stacking or integration of qubit circuitries, mechanical properties and handling.
The majority of qubit chip integration is realized in a two-dimensional (2D) architecture. Whereas 3D architecture enables more advantages like efficient interconnect routing, allowing for more compact qubit coupling geometries, reducing form factor, and increased connectivity beyond nearest-neighbor interactions. Flip-chip (FC) assembly has been demonstrated to enable 3D architecture connecting qubit chip, interposer, and readout in a sandwich-like structure. Moreover, 3D integration allows the fabrication of hosting chip circuitry without degrading the qubit performance [1]–[4]. Different material considerations have to be taken into account since qubit operational frequency is in the gigahertz range and operating temperature is in the mK range to avoid thermal excitation. Materials that possess superconducting characteristics like Indium (In), Titanium Nitride (TiN), Tantalum Nitride (TaN), and Niobium (Nb) have been discussed as potential interconnect between building blocks [3], [5]. The In bumping on Aluminum (Al) redistribution layers require under-bump metallization (UBM) layers thus introducing multiple fabrication steps before the bonding process. An alternative approach would be to use the existing Al surface to electrochemically grow Al bumps and bond the chip using thermosonic bonding (TSB) at below 150°C to form a homogeneous metal-metal interface [6], [7].
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.
As quantum computing evolves from small-scale qubit systems to more complex large-scale processors, the demand for individual qubit control and scalability will lead to the use of 3D integration and packaging technologies. Although advances in 3D integration in traditional CMOS technology are notable at room temperature, its potential in cryogenic environments, especially in quantum computing, remains largely unexplored. Superconducting qubit technology demands improvements in qubit relaxation and coherence time. Tantalum (Ta), renowned for its minimal loss, remarkable coherence time and superior stability, emerges as a promising candidate for superconducting materials. This study presents a novel approach by utilizing Ta-Ta thermo-compression bonding to create superconducting joints between wafers for vertical integration for the first time. A successful bonding temperature (500 °C) and pressure (0.3 MPa) results in the emergence of$\alpha $-tantalum, which improves the coherence time significantly as reported earlier. The shear strength test shows a bond strength of 200 MPa which is a clear indication of a good bond between the two layers. Hence, we demonstrate the feasibility of achieving 3D integration of superconducting chips using this approach, thus opening doors for inventive quantum computing architectures.
Large-scale quantum computers with more than 10510^5105 qubits will likely be built within the next decade. Trapped ions, semiconductor devices, and superconducting qubits among other physical implementations are still confined in the realm of medium-scale quantum integration (∼100\sim 100∼100 qubits); however, they show promise toward large-scale quantum integration. Building large-scale quantum processing units will require truly scalable control and measurement classical coprocessors as well as suitable wiring methods. In this blue paper, we introduce a fully vertical interconnect that will make it possible to address ∼105\sim 10^5∼105 superconducting qubits fabricated on a single silicon or sapphire chip: Pin-chip bonding. This method permits signal transmission from DC to ∼10\sim 10∼10 GHz, both at room temperature and at cryogenic temperatures down to ∼10\sim 10∼10 mK. At temperatures below ∼1\sim 1∼1 K, the on-chip wiring contact resistance is close to zero and all signal lines are in the superconducting state. High-density wiring is achieved by means of a fully vertical interconnect that interfaces the qubit array with a network of rectangular coaxial ribbon cables. Pin-chip bonding is fully compatible with classical high-density test board applications as well as with other qubit implementations.