Quantum computing relies on a blend of superposition and entanglement phenomena of qubit devices to solve problems. It promises unparalleled computational throughput that has been earmarked to surpass that of even supercomputers. While the concept of quantum computing and quantum information processing has been established, there have been challenges in the scalability of qubits and the heterogeneous integration of qubits with control, read-out electronics. With the increased number of qubit devices, there is a pressing need to incorporate the many interconnects to address the qubits. 2.5D/3D advanced wafer-level packaging provides a solution to address these needs. Currently, Nb or Nb-based metals is one of the preferred superconducting interconnects for quantum devices and circuitry routing. This paper discusses the demonstration of a room-temperature wafer-to-wafer Nb bonding process for potential 3D stacking or integration of qubit circuitries, mechanical properties and handling.
Quantum computing relies on a blend of superposition and entanglement phenomena of qubit devices to solve problems. It promises unparalleled computational throughput that has been earmarked to surpass that of even supercomputers. While the concept of quantum computing and quantum information processing has been established, there have been challenges in the scalability of qubits and the heterogeneous integration of qubits with control, read-out electronics. With the increased number of qubit devices, there is a pressing need to incorporate the many interconnects to address the qubits. 2.5D/3D advanced wafer-level packaging provides a solution to address these needs. Currently, Nb or Nb-based metals is one of the preferred superconducting interconnects for quantum devices and circuitry routing. This paper discusses the demonstration of a room-temperature wafer-to-wafer Nb bonding process for potential 3D stacking or integration of qubit circuitries, mechanical properties and handling.
3-D chip integration is considered to be the best way for further increasing the number of qubits on chip, and also for integration of qubits and readout electronics. Works have been done to stack two wafers with superconductive interconnections as a demonstration for feasibility of 3-D qubit integration.But all of them use an extra layer of adhesives, indium in particular, to join two neighboring planes.Indium is a good choice of adhesive for wafer bonding at cryogenic temperature. However, there are potential issues to employ this extra layer of adhesive. First, the critical temperature (Tc) of indium being 3.4K means it is suitable preferably for superconducting qubits, but not good enough for qubit implementations or other cryogenic that have above-4K expectations. Second, one general problem in wafer bonding is that alignment is not accurate. Adding an extra layer of anything increases the degree of misalignment. In this work, the extra adhesive layer is abandoned and two wafers are bonded by direct-bonding technique. First, niobium nitride (NbN) is chosen to be the skeleton for this 3-D structure due to its high Tc (18K) as well as its simple composition hence easy fabrication. Sputtering is the method used to fabricate such metal nitride. Sample with Tc=15.6K has been measured so far. Second, both wafer-scale and miniaturized pattern are designed to measure contact resistance of direct bonding of NbN films in room and cryogenic temperature. This work shows the potential of direct-wafer bonding in 3-D chip integration at cryogenic environment, and could further lead to scaling up of quantum processors.
Scalable quantum computing currently requires a large array of qubit integration, but present two-dimensional interconnects face challenges such as wiring congestion, electromagnetic interference, and limited cryogenic space. To overcome this challenge, implementing three-dimensional (3D) vertical architectures becomes crucial. Niobium (Nb), due to its excellent superconducting characteristics and strong fabrication process compatibility, stands out as a prime material choice. The main challenge in Nb-Nb bonding is the presence of an oxide layer at the interface, even after post-bonding annealing across various bonding methods. The native Nb oxide forms rapidly in air, creating a resistive barrier to supercurrent flow and introducing two-level system losses that degrade qubit coherence while increasing the overall thermal budget. These issues show the need for effective surface engineering to suppress oxidation during bonding. This study introduces an ultrathin gold (Au) capping layer as a passivation strategy to prevent oxygen incorporation at the Nb surface. This approach enables low-temperature Nb-Nb thermocompression bonding at 350 °C under a reduced bonding pressure of 0.495 MPa. Detailed microstructural and interfacial analyses confirm that Au passivation effectively suppresses oxide formation and hence enhances bonding uniformity and strength with keeping the superconductivity, establishing a robust route toward low-temperature, low-pressure Nb-Nb bonding for scalable 3D superconducting quantum computing architectures.
As quantum computing evolves from small-scale qubit systems to more complex large-scale processors, the demand for individual qubit control and scalability will lead to the use of 3D integration and packaging technologies. Although advances in 3D integration in traditional CMOS technology are notable at room temperature, its potential in cryogenic environments, especially in quantum computing, remains largely unexplored. Superconducting qubit technology demands improvements in qubit relaxation and coherence time. Tantalum (Ta), renowned for its minimal loss, remarkable coherence time and superior stability, emerges as a promising candidate for superconducting materials. This study presents a novel approach by utilizing Ta-Ta thermo-compression bonding to create superconducting joints between wafers for vertical integration for the first time. A successful bonding temperature (500 °C) and pressure (0.3 MPa) results in the emergence of$\alpha $-tantalum, which improves the coherence time significantly as reported earlier. The shear strength test shows a bond strength of 200 MPa which is a clear indication of a good bond between the two layers. Hence, we demonstrate the feasibility of achieving 3D integration of superconducting chips using this approach, thus opening doors for inventive quantum computing architectures.
Abstract To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspectives in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al 0.995 Cu 0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.
The majority of qubit chip integration is realized in a two-dimensional (2D) architecture. Whereas 3D architecture enables more advantages like efficient interconnect routing, allowing for more compact qubit coupling geometries, reducing form factor, and increased connectivity beyond nearest-neighbor interactions. Flip-chip (FC) assembly has been demonstrated to enable 3D architecture connecting qubit chip, interposer, and readout in a sandwich-like structure. Moreover, 3D integration allows the fabrication of hosting chip circuitry without degrading the qubit performance [1]–[4]. Different material considerations have to be taken into account since qubit operational frequency is in the gigahertz range and operating temperature is in the mK range to avoid thermal excitation. Materials that possess superconducting characteristics like Indium (In), Titanium Nitride (TiN), Tantalum Nitride (TaN), and Niobium (Nb) have been discussed as potential interconnect between building blocks [3], [5]. The In bumping on Aluminum (Al) redistribution layers require under-bump metallization (UBM) layers thus introducing multiple fabrication steps before the bonding process. An alternative approach would be to use the existing Al surface to electrochemically grow Al bumps and bond the chip using thermosonic bonding (TSB) at below 150°C to form a homogeneous metal-metal interface [6], [7].
Quantum computers perform calculations using quantum bits, or qubits, which can be made from superconducting circuits. These superconducting qubits allow direct control over device parameters while leveraging conventional Si-based fabrication techniques. MIT Lincoln Laboratory is designing and building high performance superconducting qubit devices with increased connectivity and addressability by utilizing advanced process techniques and 3D integration. Our three-tier stack architecture combines separately fabricated qubit, interposer, and routing chips with indium bump bonding. This stack contains high performance qubits, resonators, and couplers, superconducting air bridge crossovers, hard-stop spacing control, superconducting high aspect-ratio through-Si vias, and planarized superconducting routing layers. I will discuss our most recent accomplishments in the fabrication of three-tier stack devices and the effects of additional processing on the uniformity and integrity of their individual components.