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IEEE Electron Device Letters

Novel Wafer-Level Ta-Ta Direct Thermocompression Bonding for 3D Integration of Superconducting Interconnects for Scalable Quantum Computing System

Harsh Mishra, Satish Bonam, Vinit Kumar, Shiv Govind Singh

Published Sep 2, 2024• 2 citations
Publisher

Abstract

As quantum computing evolves from small-scale qubit systems to more complex large-scale processors, the demand for individual qubit control and scalability will lead to the use of 3D integration and packaging technologies. Although advances in 3D integration in traditional CMOS technology are notable at room temperature, its potential in cryogenic environments, especially in quantum computing, remains largely unexplored. Superconducting qubit technology demands improvements in qubit relaxation and coherence time. Tantalum (Ta), renowned for its minimal loss, remarkable coherence time and superior stability, emerges as a promising candidate for superconducting materials. This study presents a novel approach by utilizing Ta-Ta thermo-compression bonding to create superconducting joints between wafers for vertical integration for the first time. A successful bonding temperature (500 °C) and pressure (0.3 MPa) results in the emergence of$\alpha $-tantalum, which improves the coherence time significantly as reported earlier. The shear strength test shows a bond strength of 200 MPa which is a clear indication of a good bond between the two layers. Hence, we demonstrate the feasibility of achieving 3D integration of superconducting chips using this approach, thus opening doors for inventive quantum computing architectures.

DOI
10.1109/led.2024.3453174

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As quantum computing evolves from small-scale qubit systems to more complex large-scale processors, the demand for individual qubit control and scalability will lead to the use of 3D integration and packaging technologies. Although advances in 3D integration in traditional CMOS technology are notable at room temperature, its potential in cryogenic environments, especially in quantum computing, remains largely unexplored. Superconducting qubit technology demands improvements in qubit relaxation and coherence time. Tantalum (Ta), renowned for its minimal loss, remarkable coherence time and superior stability, emerges as a promising candidate for superconducting materials. This study presents a novel approach by utilizing Ta-Ta thermo-compression bonding to create superconducting joints between wafers for vertical integration for the first time. A successful bonding temperature (500 °C) and pressure (0.3 MPa) results in the emergence ofα\alpha α-tantalum, which improves the coherence time significantly as reported earlier. The shear strength test shows a bond strength of 200 MPa which is a clear indication of a good bond between the two layers. Hence, we demonstrate the feasibility of achieving 3D integration of superconducting chips using this approach, thus opening doors for inventive quantum computing architectures.
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To create a practical quantum computer, one must produce and incorporate around one million qubits. The greatest hurdle lies in finding a technology that allows for precise control over two-level quantum systems while enabling mass production. While achieving a high quantity of qubits is crucial, the most critical factor is qubit quality, which is measured by the number of gate operations a qubit can perform during its coherence time (also known as its lifetime). Unfortunately, qubits are susceptible to environmental disturbances, leading to the degradation of their quantum states over time. To sustain the computation process, a minimum threshold for quantum error correction is required, which is approximately 1000 times the qubit time. While researchers have managed to develop high-quality qubits, they have encountered limitations in terms of number of qubits. The methodology to address this challenge is through scalability using 2D technology at the expense of larger chip sizes, increased complexity, and subsequently, a potential compromise in qubit quality. Hence, to overcome this issue we have to look for vertical interconnects for large-scale qubit integration. Interconnects are not new they have already been used in the semiconductor industry. However, superconducting qubit is only facilitated at cryogenic temperature hence the materials that are traditionally used for electrical conductivity, like Cu and tungsten (w) are not superconducting in nature. Therefore, in this paper, we have analyzed the vertical superconducting interconnects filled with different superconducting materials using the time-dependent Ginzburg-landau equation and observed how the temperature-dependent London penetration depth results in an increase in cooper pair density or superconducting electron density.
Quantum computing relies on a blend of superposition and entanglement phenomena of qubit devices to solve problems. It promises unparalleled computational throughput that has been earmarked to surpass that of even supercomputers. While the concept of quantum computing and quantum information processing has been established, there have been challenges in the scalability of qubits and the heterogeneous integration of qubits with control, read-out electronics. With the increased number of qubit devices, there is a pressing need to incorporate the many interconnects to address the qubits. 2.5D/3D advanced wafer-level packaging provides a solution to address these needs. Currently, Nb or Nb-based metals is one of the preferred superconducting interconnects for quantum devices and circuitry routing. This paper discusses the demonstration of a room-temperature wafer-to-wafer Nb bonding process for potential 3D stacking or integration of qubit circuitries, mechanical properties and handling.
Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining 20 μm20\,μ\mathrm{m}20μm thick indium bumps on the control chip with 200 nm200\,\mathrm{nm}200nm thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of T1=(159±14) μsT_1=(159\pm14)\,μ\mathrm{s}T1​=(159±14)μs and T2,echo=(294±42) μsT_{\mathrm{2,echo}}=(294\pm42)\,μ\mathrm{s}T2,echo​=(294±42)μs, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to (20±12) μrad(20\pm12)\,μ\mathrm{rad}(20±12)μrad. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.
3-D chip integration is considered to be the best way for further increasing the number of qubits on chip, and also for integration of qubits and readout electronics. Works have been done to stack two wafers with superconductive interconnections as a demonstration for feasibility of 3-D qubit integration.But all of them use an extra layer of adhesives, indium in particular, to join two neighboring planes.Indium is a good choice of adhesive for wafer bonding at cryogenic temperature. However, there are potential issues to employ this extra layer of adhesive. First, the critical temperature (Tc) of indium being 3.4K means it is suitable preferably for superconducting qubits, but not good enough for qubit implementations or other cryogenic that have above-4K expectations. Second, one general problem in wafer bonding is that alignment is not accurate. Adding an extra layer of anything increases the degree of misalignment. In this work, the extra adhesive layer is abandoned and two wafers are bonded by direct-bonding technique. First, niobium nitride (NbN) is chosen to be the skeleton for this 3-D structure due to its high Tc (18K) as well as its simple composition hence easy fabrication. Sputtering is the method used to fabricate such metal nitride. Sample with Tc=15.6K has been measured so far. Second, both wafer-scale and miniaturized pattern are designed to measure contact resistance of direct bonding of NbN films in room and cryogenic temperature. This work shows the potential of direct-wafer bonding in 3-D chip integration at cryogenic environment, and could further lead to scaling up of quantum processors.
An advanced quantum processor requires millions of qubits but is at present limited in scalability due to limitations in the wiring of qubits. A 2.5D silicon (Si) interposer provides an attractive solution in enabling the scalability of the qubit devices. However, some qubits, like the superconducting qubits and solid-state spin-orbit qubits, operate in cryogenic temperatures below 1K. Copper (Cu) interconnects in conventional Si interposers are not superconductive in nature. As such, these metals contribute to losses and result in resistive heating, which can undesirably increase the temperature of the qubits during operation. This paper reports the full demonstration and electrical characterization of a cryogenic interposer with superconducting interconnects and TSV, using CMOS compatible materials like Aluminium (Al), Titanium (Ti), Titanium Nitride (TiN) and Tantalum (Ta).