Quantum computing architectures with ten or more quantum bits (qubits) have been implemented using trapped ions and superconducting devices. The next milestone in the quest for a quantum computer is the realization of quantum error correction codes. Such codes will require a large number of qubits that must be controlled and measured by means of classical electronics. This scaling up leads to a number of problems and sources of error that must be accounted for in order to have an operational system. \n \nOne architectural aspect requiring immediate attention is the realization of a suitable interconnect between the quantum and classical hardware. Our proposed solution to this wiring problem is the quantum socket, a three-dimensional wiring method for qubits with superior performance as compared to two-dimensional methods based on wire bonding. The quantum socket also provides a means to counteract another scaling problem, the coupling of qubits to unwanted cavity modes resulting in coherent leakage error. By following our proposed wiring methodologies, half-wave fencing or antinode pinning, we show how the error due to leakage can be mitigated to orders of magnitude below current state-of-the-art error probabilities.
Quantum computing architectures with ten or more quantum bits (qubits) have been implemented using trapped ions and superconducting devices. The next milestone in the quest for a quantum computer is the realization of quantum error correction codes. Such codes will require a large number of qubits that must be controlled and measured by means of classical electronics. This scaling up leads to a number of problems and sources of error that must be accounted for in order to have an operational system. \n \nOne architectural aspect requiring immediate attention is the realization of a suitable interconnect between the quantum and classical hardware. Our proposed solution to this wiring problem is the quantum socket, a three-dimensional wiring method for qubits with superior performance as compared to two-dimensional methods based on wire bonding. The quantum socket also provides a means to counteract another scaling problem, the coupling of qubits to unwanted cavity modes resulting in coherent leakage error. By following our proposed wiring methodologies, half-wave fencing or antinode pinning, we show how the error due to leakage can be mitigated to orders of magnitude below current state-of-the-art error probabilities.
Reimagining and miniaturizing the huge machines of the World War II era was a great step in the history of computing. Now quantum computers face a similar developmental step, on the way to tomorrow's compact, scalable systems. In analogy with sockets in traditional electronics, the authors present a link for classical control hardware and solid-state qubits, with exceptional properties at microwave frequencies and cryogenic temperatures. This technology should bring us within a few years to a key milestone in quantum computing: quantum error-correction implemented for hundreds of physical qubits.
Reaching fault tolerance means scaling qubit counts by orders of magnitude, a jump that conventional superconducting architectures cannot sustain without solving the so-called `wiring problem'. Global control sidesteps this bottleneck, but implementing quantum error correction (QEC) on previously proposed global architectures incurs extremely steep overhead costs, due to the need for separate correction procedures for the computational and auxiliary qubits that comprise the global device. We resolve this by introducing the first globally-controlled architecture with zero qubit overhead. Every physical qubit is a computational qubit, and thus, every qubit is protected under a single error correcting scheme. We identify a class of cyclic stabilizer codes realizable through global iSWAP and single-qubit gates, yielding QEC thresholds nearly seven orders of magnitude larger than previous estimates for globally-controlled arrays. We further show these thresholds improve systematically as the global architecture is augmented with a limited amount of local measurement sites, demonstrating a trade-off between wiring simplicity and fault-tolerant performance.
Abstract Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.
A quantum computer will use the properties of quantum physics to solve certain computational problems much faster than otherwise possible. One promising potential implementation is to use superconducting quantum bits in the circuit quantum electrodynamics (cQED) architecture. There, the low energy states of a nonlinear electronic oscillator are isolated and addressed as a qubit. These qubits are capacitively coupled to the modes of a microwave-frequency transmission line resonator which serves as a quantum communication bus. Microwave electrical pulses are applied to the resonator to manipulate or measure the qubit state. State control is calibrated using diagnostic sequences that expose systematic errors. Hybridization of the resonator with the qubit gives it a nonlinear response when driven strongly, useful for amplifying the measurement signal to enhance accuracy. Qubits coupled to the same bus may coherently interact with one another via the exchange of virtual photons. A two-qubit conditional phase gate mediated by this interaction can deterministically entangle its targets, and is used to generate two-qubit Bell states and three-qubit GHZ states. These three-qubit states are of particular interest because they redundantly encode quantum information. They are the basis of the quantum repetition code prototypical of more sophisticated schemes required for quantum computation. Using a three-qubit Toffoli gate, this code is demonstrated to autonomously correct either bit- or phase-flip errors. Despite observing the expected behavior, the overall fidelity is low because of decoherence. A superior implementation of cQED replaces the transmission-line resonator with a three-dimensional box mode, increasing lifetimes by an order of magnitude. In-situ qubit frequency control is enabled with control lines, which are used to fully characterize and control the system Hamiltonian.
Large-scale quantum computers with more than 105 qubits will likely be built within the next decade. Trapped ions, semiconductor devices, and superconducting qubits among other physical implementations are still confined in the realm of medium-scale quantum integration (∼100 qubits); however, they show promise toward large-scale quantum integration. Building large-scale quantum processing units will require truly scalable control and measurement classical coprocessors as well as suitable wiring methods. In this blue paper, we introduce a fully vertical interconnect that will make it possible to address ∼105 superconducting qubits fabricated on a single silicon or sapphire chip: Pin-chip bonding. This method permits signal transmission from DC to ∼10 GHz, both at room temperature and at cryogenic temperatures down to ∼10 mK. At temperatures below ∼1 K, the on-chip wiring contact resistance is close to zero and all signal lines are in the superconducting state. High-density wiring is achieved by means of a fully vertical interconnect that interfaces the qubit array with a network of rectangular coaxial ribbon cables. Pin-chip bonding is fully compatible with classical high-density test board applications as well as with other qubit implementations.
Quantum computing holds the promise of solving problems that are intractable for classical computers, with applications ranging from optimization and materials simulation to cryptography. It achieves this by leveraging the exponentially scaling dimensionality of the space encoding quantum information and by executing algorithms on quantum registers in superposition states – a feature often referred to as quantum parallelism. However, while encoding information in computational units capable of exploring a continuous set of quantum states enables exponential scaling of computational power with system size, quantum systems are also more susceptible to errors than their classical counterparts. These errors take the form of both control errors, where miscalibration of the control pulses causes coherent errors on the qubit states, as well as incoherent errors due to energy relaxation and dephasing. Scaling quantum systems to run useful algorithms involving hundreds or thousands of logical qubits will require quantum error correction. In this approach, quantum information is redundantly encoded across an entangled state of many physical qubits. This has enabled experimental demonstrations across various platforms – including ion traps, superconducting circuits, and neutral atoms – showing that encoded quantum states can be preserved beyond the coherence times of the constituting physical qubits. However, quantum state preservation is only one component needed for scalable quantum computing. To execute algorithms, it is also necessary to implement quantum gates on and between encoded qubits, in a way that maintains fault tolerance by preserving the ability to correct errors as they occur during the computation. In the first part of this thesis, we demonstrate the implementation of an error-corrected quantum operation that entangles two logical qubits. This is achieved by performing lattice surgery on a distance-three surface code qubit, resulting in a logical Bell state encoded in distance-three repetition codes, which enable the correction of single bit-flip errors. We further introduce techniques to benchmark and characterize the performance of logical operations, including applying the protocol to arbitrary logical input states and performing logical quantum process tomography. Together, these results constitute one of the first realizations of error-corrected lattice surgery in superconducting circuits. While quantum error correction can correct errors provided they occur with sufficiently low frequency, it may fail when many qubits experience errors simultaneously. In the second part of this thesis, we therefore shift focus to a specific error mechanism known to cause correlated errors in superconducting circuits – quasiparticle-induced decoherence. In this case, various forms of energy deposition on the quantum device can break Cooper pairs into quasiparticles, which may subsequently diffuse to the tunnel junction and interact with the qubit state, thereby causing decoherence. In this thesis, we investigate the impact of quasiparticle tunneling on qubit performance, with a focus on infrared-induced quasiparticles. We compare the sensitivity of niobium-based qubits to those made from tantalum – a material that has gained interest in recent years following demonstrations of qubits with improved coherence times based on this material. Using a thermal radiator source, we show that the performance of tantalum qubits may be limited by infrared-induced quasiparticles in typical superconducting circuit experimental setups. By employing both ambient and in-line infrared filters, we investigate the effectiveness of different filtering strategies and develop best practices for engineering cryogenic environments for superconducting quantum processors. The results presented in this thesis contribute to the advancement of quantum computing based on superconducting circuits by implementing and characterizing quantum error-corrected operations, and by investigating quasiparticles as a source of decoherence, along with strategies to improve infrared filtering and signal conditioning in cryogenic environments for future fault-tolerant quantum computing.