Abstract Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.
Abstract Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.
Quantum error correction will be a necessary component towards realizing scalable quantum computers with physical qubits. Theoretically, it is possible to perform arbitrarily long computations so long as the error rate is below a threshold value. The two-dimensional surface code permits relatively high fault-tolerant thresholds at the ∼ 1% level, and only requires a latticed network of qubits with nearest-neighbor interactions. I will discuss our implementation of a sub-section of the larger fabric using three transmon qubits and two linking microwave resonators. We demonstrate high-fidelity control over the sub-section surface code strand, verified via quantum prcoess tomography and randomized benchmarking experiments. Our fixed-frequency qubit approach relies on the two-qubit cross-resonance microwave driving interaction, which is now one of many microwave-based entangling gate protocols. I will also discuss the prospects to scale to surface code plaquette level experiments.
Superconducting circuits have been demonstrated at the ~50 qubit scale, with gate fidelities approaching the thresholds required for error correction using surface codes. It is generally considered that maintaining and improving this performance while scaling to >100 qubits will require 3D integration of control wiring, and techniques to prevent or mitigate the effects of unwanted electromagnetic modes which emerge in the circuit environment at larger scales. At the present time, no single design has emerged as the clear scaling "winner'', and many different modalities are being explored. In this thesis, we describe one potential scaling architecture for superconducting circuits, which is based on a unit cell containing a set of controllable, measurable qubits. In analogy to the unit cell of a crystal, this unit cell can be tiled, in this case to form 2D arrays of individually controllable and measurable qubits. This is enabled by three key technologies: 3D integrated off-chip control wiring, reverse-side readout resonators, and inductive shunting of the device enclosure with micromachined pillars. To validate this approach, we design and build a demonstration device featuring four transmon qubits and containing within it a single unit cell of the architecture. The device construction involves the fabrication of reverse-side circuits and the use of novel CNC drilling of the circuit substrate. We measure coherence times and single-qubit gate fidelities comparable with the state-of-the-art for transmon qubits (avg. T1 = 149 µs, avg. echoed pure dephasing T2 = 189 µs, avg. F > 99.98%), establishing that the design is compatible with high coherence. An important feature of the design is that the infinite construct formed by tiling the plane with the unit cell possesses a cutoff frequency, below which the circuit environment cannot sustain any electromagnetic modes. We develop models to predict this cutoff frequency, and predict that environment mediated crosstalk between qubits inside this structure decays exponentially with spatial separation. This crosstalk can be viewed as being mediated by evanescent waveguide modes, or by bound states formed by the interaction of qubits with the environmental modes around the cutoff. Both models provide quantitative predictions for the rate of crosstalk decay, which are shown to be in good agreement. We propose this architecture as a promising candidate for building 2D arrays of hundreds or thousands of nearest neighbour coupled superconducting qubits, which could provide a testbed of quantum error correction schemes such as the surface code.
This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.
Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from O(d) in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal S gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.
Facilitating the ability to achieve logical qubit error rates below physical qubit error rates, error correction is anticipated to play an important role in scaling quantum computers. While many algorithms require millions of physical qubits to be executed with error correction, current superconducting qubit systems contain only hundreds of physical qubits. One of the most promising codes on the superconducting qubit platform is the surface code, requiring a realistically attainable error threshold and the ability to perform universal fault-tolerant quantum computing with local operations via lattice surgery and magic state injection. Surface code architectures easily generalize to single-chip planar layouts, however space and control hardware constraints point to limits on the number of qubits that can fit on one chip. Additionally, the planar routing on single-chip architectures leads to serialization of commuting gates and strain on classical decoding caused by large ancilla patches. A distributed multi-chip architecture utilizing the surface code can potentially solve these problems if one can optimize inter-chip gates, manage collisions in networking between chips, and minimize routing hardware costs. We propose QuIRC, a superconducting Quantum Interface Routing Card for Lattice Surgery between surface code modules inside of a single dilution refrigerator. QuIRC improves scaling by allowing connection of many modules, increases ancilla connectivity of surface code lattices, and offers improved transpilation of Pauli-based surface code circuits. QuIRC employs in-situ Entangled Pair (EP) generation protocols for communication. We explore potential topological layouts of QuIRC based on superconducting hardware fabrication constraints, and demonstrate reductions in ancilla patch size by up to 77.8%, and in layer transpilation size by 51.9% when compared to the single-chip case.
Quantum computing architectures with ten or more quantum bits (qubits) have been implemented using trapped ions and superconducting devices. The next milestone in the quest for a quantum computer is the realization of quantum error correction codes. Such codes will require a large number of qubits that must be controlled and measured by means of classical electronics. This scaling up leads to a number of problems and sources of error that must be accounted for in order to have an operational system. \n \nOne architectural aspect requiring immediate attention is the realization of a suitable interconnect between the quantum and classical hardware. Our proposed solution to this wiring problem is the quantum socket, a three-dimensional wiring method for qubits with superior performance as compared to two-dimensional methods based on wire bonding. The quantum socket also provides a means to counteract another scaling problem, the coupling of qubits to unwanted cavity modes resulting in coherent leakage error. By following our proposed wiring methodologies, half-wave fencing or antinode pinning, we show how the error due to leakage can be mitigated to orders of magnitude below current state-of-the-art error probabilities.