Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Developing a tileable superconducting circuit for quantum computation

Peter Spring

Published Jan 1, 2021• 0 citations
Publisher

Abstract

Superconducting circuits have been demonstrated at the ~50 qubit scale, with gate fidelities approaching the thresholds required for error correction using surface codes. It is generally considered that maintaining and improving this performance while scaling to >100 qubits will require 3D integration of control wiring, and techniques to prevent or mitigate the effects of unwanted electromagnetic modes which emerge in the circuit environment at larger scales. At the present time, no single design has emerged as the clear scaling "winner'', and many different modalities are being explored. In this thesis, we describe one potential scaling architecture for superconducting circuits, which is based on a unit cell containing a set of controllable, measurable qubits. In analogy to the unit cell of a crystal, this unit cell can be tiled, in this case to form 2D arrays of individually controllable and measurable qubits. This is enabled by three key technologies: 3D integrated off-chip control wiring, reverse-side readout resonators, and inductive shunting of the device enclosure with micromachined pillars. To validate this approach, we design and build a demonstration device featuring four transmon qubits and containing within it a single unit cell of the architecture. The device construction involves the fabrication of reverse-side circuits and the use of novel CNC drilling of the circuit substrate. We measure coherence times and single-qubit gate fidelities comparable with the state-of-the-art for transmon qubits (avg. T1 = 149 µs, avg. echoed pure dephasing T2 = 189 µs, avg. F > 99.98%), establishing that the design is compatible with high coherence. An important feature of the design is that the infinite construct formed by tiling the plane with the unit cell possesses a cutoff frequency, below which the circuit environment cannot sustain any electromagnetic modes. We develop models to predict this cutoff frequency, and predict that environment mediated crosstalk between qubits inside this structure decays exponentially with spatial separation. This crosstalk can be viewed as being mediated by evanescent waveguide modes, or by bound states formed by the interaction of qubits with the environmental modes around the cutoff. Both models provide quantitative predictions for the rate of crosstalk decay, which are shown to be in good agreement. We propose this architecture as a promising candidate for building 2D arrays of hundreds or thousands of nearest neighbour coupled superconducting qubits, which could provide a testbed of quantum error correction schemes such as the surface code.

DOI
10.5287/ora-xvkwpvrnn

Related papers

High coherence and low cross-talk in a tileable 3D integrated superconducting circuit architecture

Peter Spring, Shuxiang Cao, Takahiro Tsunoda +11 more

We report high qubit coherence as well as low cross-talk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to two-dimensional (2D) lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring nongalvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T 1 = 149(38) μs, pure echoed dephasing times T ϕ, e = 189(34) μs, and single-qubit gate fidelities F = 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.

arXiv:2107.11140•Science Advances•Apr 22, 2022•43 citations

Crosstalk Dispersion and Spatial Scaling in Superconducting Qubit Arrays

Mohammed Alghadeer, Simon Pettersson Fors, Shuxiang Cao +5 more

Crosstalk between qubits fundamentally limits the scalability of quantum processors, necessitating physics-based models that can handle the complexity of large qubit arrays. Here, we develop a comprehensive theoretical and experimental framework that captures residual interactions between both adjacent and non-adjacent qubits in fixed-frequency transmon lattices. The model integrates the combined effects of exponential localization in banded capacitance matrices, suppression of virtual couplings through detuning products across intermediate modes, and evanescent decay of below-cutoff electromagnetic fields, yielding predictive scaling relations for coupling strength as a function of spatial separation and spectral detuning. Experimental characterization of a $4 \times 4$ superconducting-qubit lattice with inductive shunt pillars reveals exponential spatial decay and frequency-dependent suppression consistent with theoretical predictions, achieving quantitative agreement for all nearest-neighbor couplings across the \qtyrange[range-phrase = --, range-units = single]{4}{6}{\giga\hertz} operating range. Our results show that standard dispersive Hamiltonian approximations systematically overestimate long-range coupling when spatial and spectral dependencies are neglected; these errors propagate into circuit simulation and design strategies. Our framework provides design guidance for crosstalk mitigation in larger-scale quantum processors under realistic fabrication constraints, addressing a bottleneck in scalability.

quant-pharXiv:2512.18148•Physical Review Research•Dec 23, 2025•0 citations

Low crosstalk in a scalable superconducting quantum lattice

Mohammed Alghadeer, Shuxiang Cao, Simone D Fasciati +5 more

Abstract Superconducting quantum circuits are a key platform for advancing quantum information processing and simulation. Scaling efforts currently encounter challenges such as Josephson-junction fabrication yield, design frequency targeting, and long-range crosstalk arising both from spurious microwave modes and intrinsic interactions between qubits. We demonstrate a scalable 4x4 square lattice with low crosstalk, comprising 16 fixed-frequency transmon qubits with nearest-neighbor capacitive coupling that is implemented in a tileable, 3D-integrated circuit architecture with off-chip inductive shunting to mitigate spurious enclosure modes. We report on the design and comprehensive characterization, and show that our implementation achieves targeted device parameters with very low frequency spreads, long-range parasitic couplings and simultaneous single-qubit gate errors across the device. Our results provide a promising pathway toward a scalable superconducting square lattice topology for quantum error correction and simulation.

arXiv:2505.22276•EPJ Quantum Technology•Jan 26, 2026•3 citations

Unified Architecture for Scalable Quantum Computing: A Modular Superconducting Platform with Digital Twin Integration

Bernecer Martinez Reyes

This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.

•Mar 11, 2026•0 citations

Development of a coaxial circuit QED architecture for quantum computing

Joseph Rahamim

Superconducting circuit QED is a promising approach for building a quantum computer. In order to realise superconducting circuits at a sufficient scale for useful near-term applications, an architecture with an extensible design is required which implements good connectivity between qubits, and allows for selective readout and control of the qubits without introducing detrimental crosstalk or decoherence. This thesis describes the development of a new coaxial circuit QED architecture that fulfils this requirement of extensibility by incorporating out-of-plane wiring into the sample holder. Single-qubit unit cells consisting of a transmon qubit and readout resonator with coaxial geometries are fabricated on opposing sides of a substrate, and selective control and readout of the qubits is achieved via a capacitance to coaxial wiring built into the device enclosure. Unit cells of qubit and resonator can be arranged in a 2D array without modification of the wiring scheme. A single-qubit unit cell of this architecture is used to implement dispersive circuit QED, and a full characterisation of the Hamiltonian is performed. The device is shown to have parameters comparable to those found in other approaches, such as a coupling between qubit-resonator of ~100 MHz and a coherence time of order ~10 µs. The extension of this scheme to 2D arrays of qubits is then presented, and realizations of two-qubits gates are demonstrated with fidelities all above 87% on a four qubit device. Further evaluations are performed on multi-qubit devices, including a characterisation of the drive isolation of the mode-matched drive ports, finding values in the range of 50 dB and 30 dB for measurement and control respectively. Similarly, the cross coupling between circuits is shown to have values ~2% of the coupling within a unit cell. The effective circuit temperatures are measured, finding typical values of ~100 mK, and the techniques of spin-locking and T2 spectroscopy are employed to probe the noise environment. Finally the architecture is extended to incorporate frequency tuning of qubits with gradiometric SQUID loops by way of off-chip flux bias lines (FBLs). These lines are used to tune qubits with a signal isolation of >99%. Furthermore, the ability of these FBLs to dynamically control the qubit frequency is shown by demonstrating switching of the frequency on a nanosecond time-scale, and parametric driving over a frequency range of gigahertz.

•Jan 1, 2019•0 citations

Pseudo-2D superconducting quantum computing circuit for the surface code: proposal and preliminary tests

Hiroto Mukai, Keiichi Sakata, Simon J. Devitt +4 more

Abstract Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.

arXiv:1902.07911•New Journal of Physics•Apr 1, 2020•28 citations
Superconducting circuits have been demonstrated at the ~50 qubit scale, with gate fidelities approaching the thresholds required for error correction using surface codes. It is generally considered that maintaining and improving this performance while scaling to >100 qubits will require 3D integration of control wiring, and techniques to prevent or mitigate the effects of unwanted electromagnetic modes which emerge in the circuit environment at larger scales. At the present time, no single design has emerged as the clear scaling "winner'', and many different modalities are being explored. In this thesis, we describe one potential scaling architecture for superconducting circuits, which is based on a unit cell containing a set of controllable, measurable qubits. In analogy to the unit cell of a crystal, this unit cell can be tiled, in this case to form 2D arrays of individually controllable and measurable qubits. This is enabled by three key technologies: 3D integrated off-chip control wiring, reverse-side readout resonators, and inductive shunting of the device enclosure with micromachined pillars. To validate this approach, we design and build a demonstration device featuring four transmon qubits and containing within it a single unit cell of the architecture. The device construction involves the fabrication of reverse-side circuits and the use of novel CNC drilling of the circuit substrate. We measure coherence times and single-qubit gate fidelities comparable with the state-of-the-art for transmon qubits (avg. T1 = 149 µs, avg. echoed pure dephasing T2 = 189 µs, avg. F > 99.98%), establishing that the design is compatible with high coherence. An important feature of the design is that the infinite construct formed by tiling the plane with the unit cell possesses a cutoff frequency, below which the circuit environment cannot sustain any electromagnetic modes. We develop models to predict this cutoff frequency, and predict that environment mediated crosstalk between qubits inside this structure decays exponentially with spatial separation. This crosstalk can be viewed as being mediated by evanescent waveguide modes, or by bound states formed by the interaction of qubits with the environmental modes around the cutoff. Both models provide quantitative predictions for the rate of crosstalk decay, which are shown to be in good agreement. We propose this architecture as a promising candidate for building 2D arrays of hundreds or thousands of nearest neighbour coupled superconducting qubits, which could provide a testbed of quantum error correction schemes such as the surface code.
We report high qubit coherence as well as low cross-talk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to two-dimensional (2D) lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring nongalvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T 1 = 149(38) μs, pure echoed dephasing times T ϕ, e = 189(34) μs, and single-qubit gate fidelities F = 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.
Crosstalk between qubits fundamentally limits the scalability of quantum processors, necessitating physics-based models that can handle the complexity of large qubit arrays. Here, we develop a comprehensive theoretical and experimental framework that captures residual interactions between both adjacent and non-adjacent qubits in fixed-frequency transmon lattices. The model integrates the combined effects of exponential localization in banded capacitance matrices, suppression of virtual couplings through detuning products across intermediate modes, and evanescent decay of below-cutoff electromagnetic fields, yielding predictive scaling relations for coupling strength as a function of spatial separation and spectral detuning. Experimental characterization of a 4×44 \times 44×4 superconducting-qubit lattice with inductive shunt pillars reveals exponential spatial decay and frequency-dependent suppression consistent with theoretical predictions, achieving quantitative agreement for all nearest-neighbor couplings across the \qtyrange[range-phrase = --, range-units = single]{4}{6}{\giga\hertz} operating range. Our results show that standard dispersive Hamiltonian approximations systematically overestimate long-range coupling when spatial and spectral dependencies are neglected; these errors propagate into circuit simulation and design strategies. Our framework provides design guidance for crosstalk mitigation in larger-scale quantum processors under realistic fabrication constraints, addressing a bottleneck in scalability.
Abstract Superconducting quantum circuits are a key platform for advancing quantum information processing and simulation. Scaling efforts currently encounter challenges such as Josephson-junction fabrication yield, design frequency targeting, and long-range crosstalk arising both from spurious microwave modes and intrinsic interactions between qubits. We demonstrate a scalable 4x4 square lattice with low crosstalk, comprising 16 fixed-frequency transmon qubits with nearest-neighbor capacitive coupling that is implemented in a tileable, 3D-integrated circuit architecture with off-chip inductive shunting to mitigate spurious enclosure modes. We report on the design and comprehensive characterization, and show that our implementation achieves targeted device parameters with very low frequency spreads, long-range parasitic couplings and simultaneous single-qubit gate errors across the device. Our results provide a promising pathway toward a scalable superconducting square lattice topology for quantum error correction and simulation.
This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.
Superconducting circuit QED is a promising approach for building a quantum computer. In order to realise superconducting circuits at a sufficient scale for useful near-term applications, an architecture with an extensible design is required which implements good connectivity between qubits, and allows for selective readout and control of the qubits without introducing detrimental crosstalk or decoherence. This thesis describes the development of a new coaxial circuit QED architecture that fulfils this requirement of extensibility by incorporating out-of-plane wiring into the sample holder. Single-qubit unit cells consisting of a transmon qubit and readout resonator with coaxial geometries are fabricated on opposing sides of a substrate, and selective control and readout of the qubits is achieved via a capacitance to coaxial wiring built into the device enclosure. Unit cells of qubit and resonator can be arranged in a 2D array without modification of the wiring scheme. A single-qubit unit cell of this architecture is used to implement dispersive circuit QED, and a full characterisation of the Hamiltonian is performed. The device is shown to have parameters comparable to those found in other approaches, such as a coupling between qubit-resonator of ~100 MHz and a coherence time of order ~10 µs. The extension of this scheme to 2D arrays of qubits is then presented, and realizations of two-qubits gates are demonstrated with fidelities all above 87% on a four qubit device. Further evaluations are performed on multi-qubit devices, including a characterisation of the drive isolation of the mode-matched drive ports, finding values in the range of 50 dB and 30 dB for measurement and control respectively. Similarly, the cross coupling between circuits is shown to have values ~2% of the coupling within a unit cell. The effective circuit temperatures are measured, finding typical values of ~100 mK, and the techniques of spin-locking and T2 spectroscopy are employed to probe the noise environment. Finally the architecture is extended to incorporate frequency tuning of qubits with gradiometric SQUID loops by way of off-chip flux bias lines (FBLs). These lines are used to tune qubits with a signal isolation of >99%. Furthermore, the ability of these FBLs to dynamically control the qubit frequency is shown by demonstrating switching of the frequency on a nanosecond time-scale, and parametric driving over a frequency range of gigahertz.
Abstract Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.