High coherence and low cross-talk in a tileable 3D integrated superconducting circuit architecture
Peter Spring, Shuxiang Cao, Takahiro Tsunoda, Giulio Campanaro, Simone D Fasciati, James Wills, Mustafa S. Bakr, Vivek Chidambaram, Boris Shteynas, Lewis G. Carpenter, Paul C. Gow, James C. Gates, Brian Vlastakis, Peter Leek
We report high qubit coherence as well as low cross-talk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to two-dimensional (2D) lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring nongalvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T 1 = 149(38) μs, pure echoed dephasing times T ϕ, e = 189(34) μs, and single-qubit gate fidelities F = 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.
We report high qubit coherence as well as low cross-talk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to two-dimensional (2D) lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring nongalvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T 1 = 149(38) μs, pure echoed dephasing times T ϕ, e = 189(34) μs, and single-qubit gate fidelities F = 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.
Superconducting circuits have been demonstrated at the ~50 qubit scale, with gate fidelities approaching the thresholds required for error correction using surface codes. It is generally considered that maintaining and improving this performance while scaling to >100 qubits will require 3D integration of control wiring, and techniques to prevent or mitigate the effects of unwanted electromagnetic modes which emerge in the circuit environment at larger scales. At the present time, no single design has emerged as the clear scaling "winner'', and many different modalities are being explored. In this thesis, we describe one potential scaling architecture for superconducting circuits, which is based on a unit cell containing a set of controllable, measurable qubits. In analogy to the unit cell of a crystal, this unit cell can be tiled, in this case to form 2D arrays of individually controllable and measurable qubits. This is enabled by three key technologies: 3D integrated off-chip control wiring, reverse-side readout resonators, and inductive shunting of the device enclosure with micromachined pillars. To validate this approach, we design and build a demonstration device featuring four transmon qubits and containing within it a single unit cell of the architecture. The device construction involves the fabrication of reverse-side circuits and the use of novel CNC drilling of the circuit substrate. We measure coherence times and single-qubit gate fidelities comparable with the state-of-the-art for transmon qubits (avg. T1 = 149 µs, avg. echoed pure dephasing T2 = 189 µs, avg. F > 99.98%), establishing that the design is compatible with high coherence. An important feature of the design is that the infinite construct formed by tiling the plane with the unit cell possesses a cutoff frequency, below which the circuit environment cannot sustain any electromagnetic modes. We develop models to predict this cutoff frequency, and predict that environment mediated crosstalk between qubits inside this structure decays exponentially with spatial separation. This crosstalk can be viewed as being mediated by evanescent waveguide modes, or by bound states formed by the interaction of qubits with the environmental modes around the cutoff. Both models provide quantitative predictions for the rate of crosstalk decay, which are shown to be in good agreement. We propose this architecture as a promising candidate for building 2D arrays of hundreds or thousands of nearest neighbour coupled superconducting qubits, which could provide a testbed of quantum error correction schemes such as the surface code.
Abstract Superconducting quantum circuits are a key platform for advancing quantum information processing and simulation. Scaling efforts currently encounter challenges such as Josephson-junction fabrication yield, design frequency targeting, and long-range crosstalk arising both from spurious microwave modes and intrinsic interactions between qubits. We demonstrate a scalable 4x4 square lattice with low crosstalk, comprising 16 fixed-frequency transmon qubits with nearest-neighbor capacitive coupling that is implemented in a tileable, 3D-integrated circuit architecture with off-chip inductive shunting to mitigate spurious enclosure modes. We report on the design and comprehensive characterization, and show that our implementation achieves targeted device parameters with very low frequency spreads, long-range parasitic couplings and simultaneous single-qubit gate errors across the device. Our results provide a promising pathway toward a scalable superconducting square lattice topology for quantum error correction and simulation.
Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit W state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes.
Superconducting circuits are well established as a strong candidate platform for the development of quantum computing. In order to advance to a practically useful level, architectures are needed which combine arrays of many qubits with selective qubit control and readout, without compromising on coherence. Here, we present a coaxial circuit quantum electrodynamics architecture in which qubit and resonator are fabricated on opposing sides of a single chip, and control and readout wiring are provided by coaxial wiring running perpendicular to the chip plane. We present characterization measurements of a fabricated device in good agreement with simulated parameters and demonstrating energy relaxation and dephasing times of T1 = 4.1 μs and T2 = 5.7 μs, respectively. The architecture allows for scaling to large arrays of selectively controlled and measured qubits with the advantage of all wiring being out of the plane.
Superconducting quantum circuits are typically housed in conducting enclosures in order to control their electromagnetic environment. As devices grow in physical size, the electromagnetic modes of the enclosure come down in frequency and can introduce unwanted long-range cross-talk between distant elements of the enclosed circuit. Incorporating arrays of inductive shunts such as through-substrate vias or machined pillars can suppress these effects by raising these mode frequencies. Here, we derive simple, accurate models for the modes of enclosures that incorporate such inductive-shunt arrays. We use these models to predict that cavity-mediated interqubit couplings and drive-line cross-talk are exponentially suppressed with distance for arbitrarily large quantum circuits housed in such enclosures, indicating the promise of this approach for quantum computing. We find good agreement with a finite-element simulation of an example device containing more than 400 qubits.
This work presents a comprehensive analytical and simulation-based study of superconducting quantum chip architectures, spanning both 2D planar and 3D-integrated designs. We first design and simulate a planar quantum chip layout using Qiskit Metal, which is imported into Ansys HFSS (High Frequency Structure Simulator) to construct a 3D model and perform electromagnetic simulations. A detailed analysis using Driven Modal, Eigenmode, Magnetostatic, and Q3D Capacitance Extraction solvers ensures our simulations accurately reflect physical behavior. The results are validated against analytical models from microwave engineering. pyEPR (Python Energy Participation Ratio) is used to extract key quantum metrics, including eigenfrequencies, quality factors, decoherence times, anharmonicity, cross-Kerr interactions, and participation ratios. Building on this planar design, we extend our study to a 3D-integrated flip-chip architecture featuring two superconducting qubits fabricated on separate high-resistivity silicon substrates. Using HFSS and analytical modeling, we show that detuned qubits maintain stable eigenfrequencies, quality factors, decoherence times, anharmonicity, and cross-Kerr interactions over varying substrate separation values. However, the introduction of dielectric loss tangents reduces quality factors which degrades coherence times and introduces an additional dephasing. These findings highlight the potential of 3D quantum integration, given minimal material imperfections.The planar and 3D designs together form a cohesive investigation into next-generation quantum hardware, with the 2D layout currently taped-out and under fabrication.