Computational ecosystems in which classical supercomputers and general-purpose quantum computers provide a steady increase in value-creating computation capabilities have shown immense progress in recent years. Superconducting qubit technology, in particular, has emerged as a leading candidate for realizing a scalable quantum computing platform ready for paving the way to commercial quantum advantage. However, current academic approaches in fabrication and testing of quantum devices are not scalable and have already started to limit the rapid development of the field. Novel solutions are required to tackle the combined challenge of increasing the qubit count on a quantum processor and the need to further reduce the qubit’s error rates. This, in turn, will lead to a renewed acceleration in qubit manufacturing, test and diagnostics. Here we present aspects of how to move superconducting qubit manufacturing and testing from small-scale laboratory to large-scale fabrication facility environments. To enable this transfer, two key ingredients are demonstrated: (i) A foundry-compatible fabrication process of superconducting qubits that can benefit from the advanced process control in industry-scale CMOS fabrication facilities, and (ii) an acceleration of testing and cryogenic measurement throughput by using a milli-Kelvin cryo-CMOS signal multiplexer operating in near proximity to quantum devices and integrated qubit diagnostic and benchmarking tools with end-to-end data analytics. Although some of these elements have been explored independently, co-development is crucial to enable an efficient scalable development cycle for quantum computing technology. A full development cycle consisting of scalable manufacturing, testing, and benchmarking will enable the large-scale fabrication and control of quantum computing devices and thus pave the way to commercial quantum advantage.
Computational ecosystems in which classical supercomputers and general-purpose quantum computers provide a steady increase in value-creating computation capabilities have shown immense progress in recent years. Superconducting qubit technology, in particular, has emerged as a leading candidate for realizing a scalable quantum computing platform ready for paving the way to commercial quantum advantage. However, current academic approaches in fabrication and testing of quantum devices are not scalable and have already started to limit the rapid development of the field. Novel solutions are required to tackle the combined challenge of increasing the qubit count on a quantum processor and the need to further reduce the qubit’s error rates. This, in turn, will lead to a renewed acceleration in qubit manufacturing, test and diagnostics. Here we present aspects of how to move superconducting qubit manufacturing and testing from small-scale laboratory to large-scale fabrication facility environments. To enable this transfer, two key ingredients are demonstrated: (i) A foundry-compatible fabrication process of superconducting qubits that can benefit from the advanced process control in industry-scale CMOS fabrication facilities, and (ii) an acceleration of testing and cryogenic measurement throughput by using a milli-Kelvin cryo-CMOS signal multiplexer operating in near proximity to quantum devices and integrated qubit diagnostic and benchmarking tools with end-to-end data analytics. Although some of these elements have been explored independently, co-development is crucial to enable an efficient scalable development cycle for quantum computing technology. A full development cycle consisting of scalable manufacturing, testing, and benchmarking will enable the large-scale fabrication and control of quantum computing devices and thus pave the way to commercial quantum advantage.
Quantum computing based on superconducting integrated circuits is entering a pivotal phase, transitioning from fundamental research and development to early-stage technology scaling and industrial implementation. But still, scaling superconducting quantum computing beyond kilo-qubit levels represents a formidable challenge. Novel solutions are required such as overhead reduction and more integrated solutions in Semicon-inspired workflows. This, in turn, will lead to a renewed acceleration in superconducting quantum computing development. In this proceedings paper we address two major challenges on the path to quantum advantage: the wiring bottleneck and the test and characterization bottleneck. The wiring bottleneck arises because each qubit requires multiple dedicated control lines—up to three for current transmon-based processors—making large-scale integration difficult. Dense wiring increases thermal load and electromagnetic interference, which can degrade gate fidelities below the error-correction threshold. This creates a trade-off between scaling qubit numbers and maintaining qubit quality. The test and characterization bottleneck stems from the need to calibrate and benchmark every qubit individually, a process that scales poorly with qubit count. Unlike classical transistors, qubits require complex, quantum-level tuning, dramatically expanding the calibration parameter space. Without automation and accelerated testing, this will lead to a backlog of untested chips and limit throughput between fabrication and qualification.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1, 2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Experiments with superconducting quantum processors have successfully demonstrated the basic functions needed for quantum computation and evidence of utility, albeit without a sizable array of error-corrected qubits. The realization of the full potential of quantum computing centers on achieving large scale fault-tolerant quantum computers. Science, engineering and industry advances are needed to robustly generate, sustain, and efficiently manipulate an exponentially large computational (Hilbert) space as well as supply the number and quality components needed for such a scaled system. In this article, we suggest critical areas of quantum system and ecosystem development, with respect to the handling and transmission of quantum information within and out of a cryogenic environment, that would accelerate the development of quantum computers based on superconducting circuits.
This paper proposes a fabless quantum-chip design and production architecture for superconducting quantum computing, centered on the SPICE-Q multiphysics simulation framework. The proposed ecosystem connects process-certified quantum PDKs, parameterized device cells, traceable model cards, SPICE-Q physical modeling languages, unified Q-EDA flows, foundry sign-off rules, cryogenic test feedback, and reusable quantum IP. In this model, design firms do not merely outsource fabrication; they prepare verified tape-outs under standardized process constraints and calibrated physical models. Its economic value lies in reducing repetitive device debugging, process exploration, and low-level layout effort, while its feasibility depends on PDK maturity, foundry yield, cryogenic test throughput, model-prediction accuracy, data-feedback mechanisms, and IP licensing boundaries. We argue that superconducting quantum chips can move from the current largely vertically integrated development model toward a fabless-foundry ecosystem only when hardware design is supported by standardized, verifiable, and reusable software and process interfaces. The required pillars are certified PDKs, PCell-based parameterized design, SPICE-Q cross-physics simulation, end-to-end Q-EDA automation, and a tradable quantum-IP market. By adapting lessons from the classical semiconductor industry to quantum hardware, this framework defines a path toward scalable, manufacturable, and commercially reusable superconducting quantum-chip design.
Abstract As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T 1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.