Novel approaches in high throughput testing and overhead reduction such as global control to narrow the gap to quantum advantage
Thorsten Last, Sibasish Mishra, Timo R. van Abswoude, Anna Shchygol, Gerben Erens, Kelvin Loh, Garrelt Alberts, Michiel Adriaan Rol, Daniel B. Szombati, Michele Dallari, Alessio Pirastu
Quantum computing based on superconducting integrated circuits is entering a pivotal phase, transitioning from fundamental research and development to early-stage technology scaling and industrial implementation. But still, scaling superconducting quantum computing beyond kilo-qubit levels represents a formidable challenge. Novel solutions are required such as overhead reduction and more integrated solutions in Semicon-inspired workflows. This, in turn, will lead to a renewed acceleration in superconducting quantum computing development. In this proceedings paper we address two major challenges on the path to quantum advantage: the wiring bottleneck and the test and characterization bottleneck. The wiring bottleneck arises because each qubit requires multiple dedicated control lines—up to three for current transmon-based processors—making large-scale integration difficult. Dense wiring increases thermal load and electromagnetic interference, which can degrade gate fidelities below the error-correction threshold. This creates a trade-off between scaling qubit numbers and maintaining qubit quality. The test and characterization bottleneck stems from the need to calibrate and benchmark every qubit individually, a process that scales poorly with qubit count. Unlike classical transistors, qubits require complex, quantum-level tuning, dramatically expanding the calibration parameter space. Without automation and accelerated testing, this will lead to a backlog of untested chips and limit throughput between fabrication and qualification.
Quantum computing based on superconducting integrated circuits is entering a pivotal phase, transitioning from fundamental research and development to early-stage technology scaling and industrial implementation. But still, scaling superconducting quantum computing beyond kilo-qubit levels represents a formidable challenge. Novel solutions are required such as overhead reduction and more integrated solutions in Semicon-inspired workflows. This, in turn, will lead to a renewed acceleration in superconducting quantum computing development. In this proceedings paper we address two major challenges on the path to quantum advantage: the wiring bottleneck and the test and characterization bottleneck. The wiring bottleneck arises because each qubit requires multiple dedicated control lines—up to three for current transmon-based processors—making large-scale integration difficult. Dense wiring increases thermal load and electromagnetic interference, which can degrade gate fidelities below the error-correction threshold. This creates a trade-off between scaling qubit numbers and maintaining qubit quality. The test and characterization bottleneck stems from the need to calibrate and benchmark every qubit individually, a process that scales poorly with qubit count. Unlike classical transistors, qubits require complex, quantum-level tuning, dramatically expanding the calibration parameter space. Without automation and accelerated testing, this will lead to a backlog of untested chips and limit throughput between fabrication and qualification.
Computational ecosystems in which classical supercomputers and general-purpose quantum computers provide a steady increase in value-creating computation capabilities have shown immense progress in recent years. Superconducting qubit technology, in particular, has emerged as a leading candidate for realizing a scalable quantum computing platform ready for paving the way to commercial quantum advantage. However, current academic approaches in fabrication and testing of quantum devices are not scalable and have already started to limit the rapid development of the field. Novel solutions are required to tackle the combined challenge of increasing the qubit count on a quantum processor and the need to further reduce the qubit’s error rates. This, in turn, will lead to a renewed acceleration in qubit manufacturing, test and diagnostics. Here we present aspects of how to move superconducting qubit manufacturing and testing from small-scale laboratory to large-scale fabrication facility environments. To enable this transfer, two key ingredients are demonstrated: (i) A foundry-compatible fabrication process of superconducting qubits that can benefit from the advanced process control in industry-scale CMOS fabrication facilities, and (ii) an acceleration of testing and cryogenic measurement throughput by using a milli-Kelvin cryo-CMOS signal multiplexer operating in near proximity to quantum devices and integrated qubit diagnostic and benchmarking tools with end-to-end data analytics. Although some of these elements have been explored independently, co-development is crucial to enable an efficient scalable development cycle for quantum computing technology. A full development cycle consisting of scalable manufacturing, testing, and benchmarking will enable the large-scale fabrication and control of quantum computing devices and thus pave the way to commercial quantum advantage.
This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.
Superconducting qubits are a leading platform for quantum computation, yet decoherence and scalability challenges continue to limit progress toward fault-tolerant systems. This review synthesizes research on architectures, noise sources, and error correction to clarify performance trade-offs and guide development. The transition from Transmon to Fluxonium has dramatically improved qubit performance, achieving millisecond-scale coherence times. However, this success reveals a fundamental limit of coherence now being primarily restricted by the physical properties of the materials, specifically dielectric losses occurring at the Josephson junction leads and within the surrounding materials. As overcoming these material limits becomes increasingly difficult, system-level engineering determines whether high-coherence qubits can scale.Scaling quantum systems is difficult because current cooling and control systems create too much heat and this forces a shift to integrated digital superconducting circuits and cryogenic light-based links. While these hardware challenges restrict scaling, experiments in error correction show that logical qubits can already outperform physical ones. For example, a distance-7 surface code improved logical qubit lifetime by 2.4×. Achieving practical fault tolerance, however, requires moving beyond simple error models. Future systems must combine techniques like Dynamical Decoupling and Machine Learning-based Optimal Control with dynamic classical control capable of handling complex, correlated faults such as Multi-Bit Burst Errors. Progress in materials, cryogenic system integration for control, and adaptive error management must advance together to realize scalable, high-fidelity quantum hardware.
Quantum computing stands poised to revolutionize digital hardware by offering computational capabilities that fundamentally transcend classical computing limitations. The global quantum computing market demonstrates substantial growth fueled by investments from major technology corporations as they race toward achieving practical quantum advantages. Despite formidable technical challenges—including the need for extremely low operating temperatures and error correction—significant advancements have been made in reducing error rates and increasing qubit counts. Novel architectures like Amazon's "Ocelot" cat qubits, Microsoft's topological quantum computing and Nvidia's accelerated quantum supercomputing that integrates quantum hardware with AI supercomputers address persistent challenges in error rates and qubit coherence. These developments open new frontiers in previously intractable problems across multiple domains, from cryptography to materials science and artificial intelligence. As the field progresses from the Noisy Intermediate-Scale Quantum era toward fault-tolerant quantum computing, it faces four critical challenges: scalability, error correction, quantum-classical integration, and algorithm development. Addressing these challenges will enable quantum computing to fulfill its transformative potential across industries, fundamentally reshaping computational technology.
Quantum computing is transitioning from laboratory research to industrial deployment, yet significant challenges persist: system scalability and performance, fabrication yields, and the advancement of algorithms and applications. We emphasize that in building quantum computers -- spanning quantum chips, system integration, instruction sets, algorithms, and middleware such as quantum error correction schemes -- design is everywhere. In this paper, we advocate for a holistic design perspective in quantum computing, a perspective we argue is pivotal to unlocking innovative co-design opportunities and addressing the aforementioned key challenges. To equip readers with sufficient background for exploring co-optimization opportunities, we detail how interconnected computational methods and tools collaborate to enable end-to-end quantum computer design. This coverage encompasses critical stages -- such as chip layout design automation, high-fidelity system-level simulation, Hamiltonian derivation for quantum system modeling, control pulse simulation, decoherence analysis, and physical verification and testing -- followed by quantum instruction set design. We then proceed to quantum system and software development, including quantum circuit synthesis, quantum error correction and fault tolerance, and logic verification and testing. Through these discussions, we illustrate with concrete examples -- including co-optimizing quantum instruction sets with algorithmic considerations, customizing error correction circuits to hardware-specific constraints, and streamlining quantum chip design through tailored code design, among others. We hope that the detailed end-to-end design workflow as well as these examples will foster dialogue between the hardware and software communities, ultimately facilitating the translation of meaningful research findings into future quantum hardware implementations.