As the number of qubits in superconducting quantum computers increases, the physical limitations of 2D chip layouts have become a major bottleneck in further development. The complexity of control wiring, crosstalk, and thermal load at cryogenic temperatures restrict the scalability of current chip designs.
Quantum computing based on superconducting integrated circuits is entering a pivotal phase, transitioning from fundamental research and development to early-stage technology scaling and industrial implementation. But still, scaling superconducting quantum computing beyond kilo-qubit levels represents a formidable challenge. Novel solutions are required such as overhead reduction and more integrated solutions in Semicon-inspired workflows. This, in turn, will lead to a renewed acceleration in superconducting quantum computing development. In this proceedings paper we address two major challenges on the path to quantum advantage: the wiring bottleneck and the test and characterization bottleneck. The wiring bottleneck arises because each qubit requires multiple dedicated control lines—up to three for current transmon-based processors—making large-scale integration difficult. Dense wiring increases thermal load and electromagnetic interference, which can degrade gate fidelities below the error-correction threshold. This creates a trade-off between scaling qubit numbers and maintaining qubit quality. The test and characterization bottleneck stems from the need to calibrate and benchmark every qubit individually, a process that scales poorly with qubit count. Unlike classical transistors, qubits require complex, quantum-level tuning, dramatically expanding the calibration parameter space. Without automation and accelerated testing, this will lead to a backlog of untested chips and limit throughput between fabrication and qualification.
To create a practical quantum computer, one must produce and incorporate around one million qubits. The greatest hurdle lies in finding a technology that allows for precise control over two-level quantum systems while enabling mass production. While achieving a high quantity of qubits is crucial, the most critical factor is qubit quality, which is measured by the number of gate operations a qubit can perform during its coherence time (also known as its lifetime). Unfortunately, qubits are susceptible to environmental disturbances, leading to the degradation of their quantum states over time. To sustain the computation process, a minimum threshold for quantum error correction is required, which is approximately 1000 times the qubit time. While researchers have managed to develop high-quality qubits, they have encountered limitations in terms of number of qubits. The methodology to address this challenge is through scalability using 2D technology at the expense of larger chip sizes, increased complexity, and subsequently, a potential compromise in qubit quality. Hence, to overcome this issue we have to look for vertical interconnects for large-scale qubit integration. Interconnects are not new they have already been used in the semiconductor industry. However, superconducting qubit is only facilitated at cryogenic temperature hence the materials that are traditionally used for electrical conductivity, like Cu and tungsten (w) are not superconducting in nature. Therefore, in this paper, we have analyzed the vertical superconducting interconnects filled with different superconducting materials using the time-dependent Ginzburg-landau equation and observed how the temperature-dependent London penetration depth results in an increase in cooper pair density or superconducting electron density.
Abstract Over the last decade, quantum computing has experienced significant changes and captured worldwide attention. In particular, superconducting qubits have become the leading candidates for scalable quantum computers, and a number of cryogenic materials have scientifically demonstrated their potential uses in constructing qubit chips. However, because of insufficient coherence time, establishing a robust and scalable quantum platform is still a long-term goal. Another consideration is the control circuits essential to initializing, operating and measuring the qubits. To keep noise low, control circuits in close proximity to the qubits require superior reliability in the cryogenic environment. The realization of the quantum advantage demands qubits with appropriate circuitry designs to maintain long coherence times and entanglement. In this work, we briefly summarize the current status of cryogenic materials for qubits and discuss typical cryogenic circuitry designs and integration techniques for qubit chips. In the end, we provide an assessment of the prospects of quantum computers and some other promising cryogenic materials.
This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.
Superconducting qubits are a leading platform for quantum computation, yet decoherence and scalability challenges continue to limit progress toward fault-tolerant systems. This review synthesizes research on architectures, noise sources, and error correction to clarify performance trade-offs and guide development. The transition from Transmon to Fluxonium has dramatically improved qubit performance, achieving millisecond-scale coherence times. However, this success reveals a fundamental limit of coherence now being primarily restricted by the physical properties of the materials, specifically dielectric losses occurring at the Josephson junction leads and within the surrounding materials. As overcoming these material limits becomes increasingly difficult, system-level engineering determines whether high-coherence qubits can scale.Scaling quantum systems is difficult because current cooling and control systems create too much heat and this forces a shift to integrated digital superconducting circuits and cryogenic light-based links. While these hardware challenges restrict scaling, experiments in error correction show that logical qubits can already outperform physical ones. For example, a distance-7 surface code improved logical qubit lifetime by 2.4×. Achieving practical fault tolerance, however, requires moving beyond simple error models. Future systems must combine techniques like Dynamical Decoupling and Machine Learning-based Optimal Control with dynamic classical control capable of handling complex, correlated faults such as Multi-Bit Burst Errors. Progress in materials, cryogenic system integration for control, and adaptive error management must advance together to realize scalable, high-fidelity quantum hardware.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.