Abstract Over the last decade, quantum computing has experienced significant changes and captured worldwide attention. In particular, superconducting qubits have become the leading candidates for scalable quantum computers, and a number of cryogenic materials have scientifically demonstrated their potential uses in constructing qubit chips. However, because of insufficient coherence time, establishing a robust and scalable quantum platform is still a long-term goal. Another consideration is the control circuits essential to initializing, operating and measuring the qubits. To keep noise low, control circuits in close proximity to the qubits require superior reliability in the cryogenic environment. The realization of the quantum advantage demands qubits with appropriate circuitry designs to maintain long coherence times and entanglement. In this work, we briefly summarize the current status of cryogenic materials for qubits and discuss typical cryogenic circuitry designs and integration techniques for qubit chips. In the end, we provide an assessment of the prospects of quantum computers and some other promising cryogenic materials.
Abstract Over the last decade, quantum computing has experienced significant changes and captured worldwide attention. In particular, superconducting qubits have become the leading candidates for scalable quantum computers, and a number of cryogenic materials have scientifically demonstrated their potential uses in constructing qubit chips. However, because of insufficient coherence time, establishing a robust and scalable quantum platform is still a long-term goal. Another consideration is the control circuits essential to initializing, operating and measuring the qubits. To keep noise low, control circuits in close proximity to the qubits require superior reliability in the cryogenic environment. The realization of the quantum advantage demands qubits with appropriate circuitry designs to maintain long coherence times and entanglement. In this work, we briefly summarize the current status of cryogenic materials for qubits and discuss typical cryogenic circuitry designs and integration techniques for qubit chips. In the end, we provide an assessment of the prospects of quantum computers and some other promising cryogenic materials.
Superconducting qubits based on Josephson junctions are one of the leading candidates for building a largescale quantum information processor. There have been significant advances in the performance of superconducting qubits over the past decade and there is currently rapid progress in the development of systems with up to tens of qubits. In order to build to yet larger systems, new techniques will need to be developed to address the overhead requirements for room-temperature electronics hardware and cryostat wiring for controlling and reading out large numbers of qubits. One approach to this challenge involves implementing more of the qubit control and readout in the low-temperature environment. I will describe our efforts on integrating superconducting classical digital circuitry with superconducting qubits for coherent control and readout.
Superconducting quantum circuits (SQCs), composed of superconducting capacitors, inductances, Josephson junctions, and transmission lines, exhibit macroscopic quantum effects at ultra-low temperatures. Due to the extremely low dissipation of superconductors, an important application of SQCs is superconducting qubits with long coherence time. Quantum computing based on superconducting qubits is a leading physical realization method of quantum computing, which is theoretically capable of accelerating many computational problems including quantum simulation, database searching, and optimization. In the long run, to use the power of quantum computing to its full extent, universal quantum computers should be constructed with quantum error correction. In the short term, one of the most pressing targets of the superconducting quantum computing community is to demonstrate quantum advantage using noisy intermediate-scale quantum chips. Both goals rely on the increasing of the number of coupled qubits in a quantum circuit and the quality of these qubits, which dictate the breadth and the depth of a problem it can solve, respectively. The fabrication of SQCs has adopted a few manufacturing processes from conventional integrated circuits. Quantum chips containing multiple superconducting qubits can be made and packaged on a large scale. “Quantum supremacy” has been demonstrated on a quantum chip with fifty-three qubits fabricated using the flip-chip bonding technology. However, to demonstrate quantum advantage, the quality and quantity of qubits need to increase simultaneously. Dissipative channels emerge in circuit design, material preparation, chip fabrication, and working environment, limiting the lifetime of superconducting qubits. For quantum chips with tens to hundreds of qubits, the integration will also introduce extra processing steps which may degrade the qubits, and unwanted coupling to loss channels. Most of these channels are microscopically related to materials constructing the quantum chips, chip surfaces, and material interfaces. Thus, it is important to investigate the material growth and device fabrication of SQCs, and to understand the material related loss mechanisms. This review paper investigates the material related topics in superconducting quantum circuits pertinent to the quantum computing application from a comprehensive perspective. The history of SQCs is briefly mentioned, followed by the peculiar characteristics as an engineerable quantum system, and a roadmap to quantum advantage and universal quantum computing in the next a few years. Technically, the superconducting quantum computer is compared to a Schrodinger’s cat, and can be boiled down into three parts, i.e., quantum chips, the environment, and the operating system, corresponding to the cat, the box, and the observer, respectively. The material related decoherence channels of the SQCs can be sorted into four categories; each will be discussed in details. To fabricate SQCs with minimal loss, the processing technologies are elaborated, including qubit design, material selection, surface treatments, film growth, and Josephson junction, etc. Though there are general guidelines that amorphous materials should be avoided and processing induced damage should be minimized, more is to be investigated due to the emerging of new materials and new fabrication methods. The last part presents the potential application of the superconducting quantum computer and its current state of play. SQC for quantum computing is a multi-discipline research topic, demanding joint efforts from different scientific and technical areas. Materials science and device processing will play important roles along the way to quantum practicality.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Quantum computing promises an exponentially higher computational power than classical computers; although all the building blocks have become available, certain constraints still prevent quantum advantage. The fundamental challenge in building a practical quantum computer is integrating thousands of highly coherent qubits with the control and readout electronics. The need for a high‐coherence qubit drives the effort for quantum error correction algorithms to create fault‐tolerant quantum systems. Error correction becomes tangible in a quantum processor only in large numbers of qubits. Thus, the other challenge is reducing the number of physical interconnects (coaxial lines) between the quantum–classical interface and bulky room‐temperature electronics. To interface thousands of qubits, interconnects can be reduced by bringing the control and readout electronics near the quantum processor. Cryogenic complementary metal–oxide–semiconductor (CMOS) technology has been an ideal candidate for this purpose. Integrated control and readout at cryogenic temperatures require low power dissipation circuit designs and techniques such as frequency‐division multiplexing (FDM) due to the finite cooling power of a dilution refrigerator. Herein, an overview of each building block in a superconducting quantum computer is provided, focusing on scalability. Furthermore, this article is concluded with an outlook discussing current challenges and future directions for the scalable superconducting control and readout.
In the pursuit of quantum computing, solid-state quantum systems, particularly superconducting ones, have made remarkable advancements over the past two decades. However, achieving fault-tolerant quantum computing for next-generation applications necessitates the integration of several million qubits, which presents significant challenges in terms of interconnection complexity and latency that are currently unsolvable with state-of-the-art room-temperature control and readout electronics. Recently, cryogenic integrated circuits (ICs), including CMOS radio-frequency ICs and rapid-single-flux-quantum-logic ICs, have emerged as potential alternatives to room-temperature electronics. Unlike their room-temperature counterparts, these ICs are deployed within cryostats to enhance scalability by reducing the number and length of transmission lines. Additionally, operating at cryogenic temperatures can suppress electronic noise and improve qubit control fidelity. However, for CMOS ICs specifically, circuit design uncertainties arise due to a lack of reliable models for cryogenic field effect transistors as well as issues related to severe fickle noises and power dissipation at cryogenic temperatures. This paper provides a comprehensive review of recent research on both types of cryogenic control and readout ICs but primarily focuses on the more mature CMOS technology. The discussion encompasses principles underlying control and readout techniques employed in cryogenic CMOS ICs along with their architectural designs; characterization and modeling approaches for field effect transistors under cryogenic conditions; as well as fundamental concepts pertaining to rapid single flux quantum circuits.