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A 12.8 mW/ channel cryogenic RF-AWG in 14nm FinFET for transmon qubit control

S. Chakraborty, Kevin Tien, D. Frolov, David J. Frank, Pat Rosno, Mark Yeck, John F. Bulzacchelli, Christian W. Baks, R.A. Richetta, Timothy J. Schmerbeck, D. Underwood, Joseph Glick, R. P. Robertazzi, A. Carter, Bryce Snell, D. Ramirez, Ken Inoue, Dorothy Wisnieff, Daniel Moertl, J. Betke, Scott Lekuch, John Timmerwilke, R. Joshi, A. Davies, Peilin Song, B. Gaucher, Daniel J. Friedman

Published Sep 9, 2024• 5 citations
Publisher

Abstract

A semi-autonomous cryogenic RF arbitrary waveform generator (AWG) is described which includes a custom low power digital processor, a current mode baseband filter (BBF) with passive feedback network, and a ground-referenced output stack whose quiescent to dynamic current ratio can be tuned for the desired tradeoff between distortion and power efficiency. It generates control signals between $4.3-7.5 \mathrm{GHz}$ and achieves 44 dB SFDR over a 1 GHz bandwidth with 12.8 mW power consumption.

DOI
10.1109/esserc62670.2024.10719526

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A semi-autonomous cryogenic RF arbitrary waveform generator (AWG) is described which includes a custom low power digital processor, a current mode baseband filter (BBF) with passive feedback network, and a ground-referenced output stack whose quiescent to dynamic current ratio can be tuned for the desired tradeoff between distortion and power efficiency. It generates control signals between 4.3−7.5GHz4.3-7.5 \mathrm{GHz}4.3−7.5GHz and achieves 44 dB SFDR over a 1 GHz bandwidth with 12.8 mW power consumption.
A scalable, non-multiplexed cryogenic 14-nm FinFET quantum bit (qubit) state controller (QSC) for use in the semi-autonomous control of superconducting transmon qubits is reported. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low-power current-mode single sideband upconversionI/Q{I}/{Q}I/Qmixer-based RF arbitrary waveform generator (AWG). Implemented in the 14-nm CMOS FinFET technology, the QSC generates control signals in its target 4.5–5.5-GHz-frequency range, achieving an spurious free dynamic range (SFDR) > 50 dB for a signal bandwidth of 500 MHz. With the controller operating in the 4 K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmonT1T_{1}T1​andT2T_{2}T2​coherence times were 75.7 and 73μs\mu \text{s}μs, respectively, in each case comparable to results achieved using conventional room temperature (RT) controls. In further tests with transmons, a qubit-limited error rate of 7.76 × 10−4 per Clifford gate is achieved, again comparable to the results achieved using RT controls. The QSC’s maximum RF output power is −18 dBm, and power dissipation per qubit under active control is 23 mW.
This chapter will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.
This work presents a 16-channel flux pulse generator ASIC for qubit control in 14nm FinFET technology consuming<7mW<7 \text{mW}<7mWper channel. Multiple 10b sub-DACs operating at different rates (up to1GS/s1 \text{GS} / \mathrm{s}1GS/s) are used to realize a pulse generator with 14b level resolution and IIR precompensation. A custom SERDES designed for<1mW<1 \text{mW}<1mWpower dissipation enables offchip2Gb/s2 \text{Gb} / \mathrm{s}2Gb/s(up) and250Mb/s250 \text{Mb} / \mathrm{s}250Mb/s(down) communications. Multi-qubit control is demonstrated, and measured error-per-2-qubit-gate is as low as 0.0017.
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.
This article presents a cryogenic transmon qubit state controller integrated circuit (IC) working at a temperature of 3.5 K for superconducting quantum computing (QC) applications. The qubit state controller IC comprises a polar-modulation-based XY -path driver and a current-steering digital-to-analog converter (DAC)-basedZ{Z}Z-path driver. To generate the XY -path driving pulse with arbitrary envelopes in the frequency range of 4–6 GHz, a switched-capacitor digital power amplifier (DPA) is adopted for amplitude modulation, and an injection locking local oscillator (IL-LO) with a constant-slope digital-to-time-converter (DTC) is used for open-loop phase modulation. With the proposed DPA and IL-LO, the controller can control a qubit with a compact architecture. Fabricated in the 28-nm bulk CMOS process, the controller IC occupies an active die area of 0.9 mm2 per driving channel. The controller achieves a spurious-free dynamic range (SFDR) of 40 dB for a 1 GS/s XY -path driver and an SFDR of 48 dB for a 1 GS/sZ{Z}Z-path driver at 3.5 K. The controller consumes a power of 13.7 mW per qubit. A Rabi experiment at 13.9 MHz, a Ramsey experiment at 3.09 MHz, and a T1 experiment at 15.87μs\mu \text{s}μsare conducted using the presented controller IC at 3.5 K to control the transmon superconducting qubit at 10 mK directly.
This article presents a 4 K cryo-CMOS RF-DAC based super-heterodyne transmitter for superconducting-qubit control. The transmitter integrates an RF-DAC based XY-path driver for quantum state manipulation and a current-steering DAC based Z-path driver for flux-bias control. To balance wideband frequency coverage and power consumption, the XY path separates programmable intermediate-frequency (IF) waveform synthesis from final microwave frequency translation. A 10-bit dual-mode RF-DAC first generates wide-IF control pulses, followed by a mixer for up-conversion to the qubit-frequency. By digitally selecting the non-return-to-zero (NRZ) or mixing (MIX) mode according to the target IF range, the RF-DAC exploits different Nyquist zones to extend the usable IF range without proportionally increasing the sampling clock frequency, enabling flexible and FDM-compatible qubit manipulation without increasing too much power. To mitigate RF-DAC current-cell mismatches under cryogenic operation, a mean-absolute-error (MAE)-based foreground calibration technique is proposed. The fully integrated controller is fabricated in a 28-nm CMOS process. The prototype is measured with ~1 GHz IF bandwidth and 8 GHz RF bandwidth under 46 mW power dissipation at the 4-K stage, and it achieves an SFDR of 33.24–41.62 dB within the 4–8 GHz. The ASIC is installed in a dilution refrigerator as a replacement of the classical control instrument, the experiment results further verify the functionality of the ASIC.