Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

22.2 A 16-Channel Low-Power Cryo-CMOS Flux Control Pulse Generator ASIC in 14nm FinFET Technology

Kevin Tien, David J. Frank, John F. Bulzacchelli, Pat Rosno, Daniel Moertl, John Timmerwilke, Ari Noori, Devin Underwood, Ken Inoue, Subhajit Ray, Daniel Ramirez, Timothy J. Schmerbeck, Bryce Snell, Jeremy T. Ekman, Ryan Black, Mark Yeck, Tom Haselhorst, Emma Erickson, Kevin Demsky, Christian W. Baks, Jonathan Kaus, Andrea Ruffino, Pier Andrea Francese, Andy Davies, Sudipto Chakraborty, Scott Lekuch, B. Gaucher, Bodhisatwa Sadhu, Scott M. Willenborg, D. Friedman

Published Feb 15, 2026• 3 citations
Publisher

Abstract

This work presents a 16-channel flux pulse generator ASIC for qubit control in 14nm FinFET technology consuming$<7 \text{mW}$per channel. Multiple 10b sub-DACs operating at different rates (up to$1 \text{GS} / \mathrm{s}$) are used to realize a pulse generator with 14b level resolution and IIR precompensation. A custom SERDES designed for$<1 \text{mW}$power dissipation enables offchip$2 \text{Gb} / \mathrm{s}$(up) and$250 \text{Mb} / \mathrm{s}$(down) communications. Multi-qubit control is demonstrated, and measured error-per-2-qubit-gate is as low as 0.0017.

DOI
10.1109/isscc49663.2026.11409194

Related papers

Using Cryogenic CMOS Control Electronics To Enable A Two-Qubit Cross-Resonance Gate

Devin Underwood, Glick, Joseph A., Inoue, Ken +18 more

Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS-based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two-qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single--side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates, and 17.51 IPC for two-qubit gates. A single-qubit error per gate of $ε_{\text{1Q}}$=8e-4 and two-qubit error per gate of $ε_\text{2Q}$=1.4e-2 is shown. A drive-induced Z-rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z-errors is numerically evaluated with a two-qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z-error varies linearly with pulse amplitude.

arXiv:2302.11538•Feb 22, 2023•0 citations

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology

Sudipto Chakraborty, David J. Frank, Kevin Tien +23 more

A scalable, non-multiplexed cryogenic 14-nm FinFET quantum bit (qubit) state controller (QSC) for use in the semi-autonomous control of superconducting transmon qubits is reported. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low-power current-mode single sideband upconversion${I}/{Q}$mixer-based RF arbitrary waveform generator (AWG). Implemented in the 14-nm CMOS FinFET technology, the QSC generates control signals in its target 4.5–5.5-GHz-frequency range, achieving an spurious free dynamic range (SFDR) > 50 dB for a signal bandwidth of 500 MHz. With the controller operating in the 4 K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon$T_{1}$and$T_{2}$coherence times were 75.7 and 73$\mu \text{s}$, respectively, in each case comparable to results achieved using conventional room temperature (RT) controls. In further tests with transmons, a qubit-limited error rate of 7.76 × 10−4 per Clifford gate is achieved, again comparable to the results achieved using RT controls. The QSC’s maximum RF output power is −18 dBm, and power dissipation per qubit under active control is 23 mW.

IEEE Journal of Solid-State Circuits•Sep 20, 2022•53 citations

Using Cryogenic CMOS Control Electronics To Enable A Two–Qubit Cross–Resonance Gate

Devin Underwood, Joseph Glick, Ken Inoue +17 more

Abstract Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS–based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two–qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single–side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single–qubit gates, and 17.51 IPC for two–qubit gates. A single–qubit error per gate of є1Q=8e-4 and two–qubit error per gate of є2Q=1.4e-2 is shown. A drive–induced Z–rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z–errors is numerically evaluated with a two–qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z–error varies linearly with pulse amplitude.

•Mar 29, 2023•5 citations

Challenges and Opportunities for Ultra- Low Power Design for Quantum Computing Applications

Sudipto Chakraborty

This chapter will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.

River Publishers eBooks•Jan 26, 2026•0 citations

Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate

Devin Underwood, Joseph A. Glick, Ken Inoue +18 more

Qubit control electronics composed of CMOS circuits are of critical interest for next-generation quantum computing systems. A CMOS-based application-specific integrated circuit (ASIC) fabricated in 14-nm fin field-effect transistor (FinFET) technology was used to generate and sequence qubit control wave forms and demonstrate a two-qubit cross-resonance gate between fixed-frequency transmons. The controller was thermally anchored to the T=4 K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single-side banded output frequencies between 4.5 and 5.5 GHz, with a maximum power output of −18 dBm. Randomized-benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates and 17.51 IPC for two-qubit gates. A single-qubit error per gate of ϵ1Q=8×10−4 and a two-qubit error per gate of ϵ2Q=1.4×10−2 were shown. A drive-induced Z rotation was observed by way of a rotary-echo experiment; this observation is consistent with the expected qubit behavior given the measured excess local-oscillator (LO) leakage from the CMOS chip. The effect of spurious drive-induced Z errors was numerically evaluated with a two-qubit model Hamiltonian and shown to be in good agreement with the measured RB data. The modeling results suggest that the Z error varies linearly with the pulse amplitude. Published by the American Physical Society 2024

PRX Quantum•Feb 14, 2024•31 citations

29.4 A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk CMOS with Phase-Detection Based Readout and Phase-Shifter Based Pulse Generation

Yanshu Guo, Qichun Liu, Wenqiang Huang +9 more

Cryogenic CMOS (Cryo-CMOS) ASICs have drawn increasing attention with great potential in scaling down the quantum computing (QC) platform. Recently, several cryoCMOS ASICs have been presented in the literature, including the qubit state readout ASICs [1–4] and state controller ASICs [5–8]. For readout ASICs, the quadrature down conversion architecture is widely adopted, with the power consumption ranging from 20mW [1] to 75mW [2]. Also, significant progress has been made in reducing the power consumption of qubit controllers. The controller in [5] consumes a power of <4 mW/qubit under active control, when controlling a superconducting quantum computing unit cell. Nevertheless, it remains a long-term goal to reduce the power consumption and promote the integration level of readout/controller ASICs, in consideration of the increasing requirement on qubit number and the limited cooling power provided by the dilution refrigerator.

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference•Feb 18, 2024•28 citations
This work presents a 16-channel flux pulse generator ASIC for qubit control in 14nm FinFET technology consuming<7mW<7 \text{mW}<7mWper channel. Multiple 10b sub-DACs operating at different rates (up to1GS/s1 \text{GS} / \mathrm{s}1GS/s) are used to realize a pulse generator with 14b level resolution and IIR precompensation. A custom SERDES designed for<1mW<1 \text{mW}<1mWpower dissipation enables offchip2Gb/s2 \text{Gb} / \mathrm{s}2Gb/s(up) and250Mb/s250 \text{Mb} / \mathrm{s}250Mb/s(down) communications. Multi-qubit control is demonstrated, and measured error-per-2-qubit-gate is as low as 0.0017.
Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS-based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two-qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single--side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates, and 17.51 IPC for two-qubit gates. A single-qubit error per gate of ε1Qε_{\text{1Q}}ε1Q​=8e-4 and two-qubit error per gate of ε2Qε_\text{2Q}ε2Q​=1.4e-2 is shown. A drive-induced Z-rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z-errors is numerically evaluated with a two-qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z-error varies linearly with pulse amplitude.
A scalable, non-multiplexed cryogenic 14-nm FinFET quantum bit (qubit) state controller (QSC) for use in the semi-autonomous control of superconducting transmon qubits is reported. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low-power current-mode single sideband upconversionI/Q{I}/{Q}I/Qmixer-based RF arbitrary waveform generator (AWG). Implemented in the 14-nm CMOS FinFET technology, the QSC generates control signals in its target 4.5–5.5-GHz-frequency range, achieving an spurious free dynamic range (SFDR) > 50 dB for a signal bandwidth of 500 MHz. With the controller operating in the 4 K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmonT1T_{1}T1​andT2T_{2}T2​coherence times were 75.7 and 73μs\mu \text{s}μs, respectively, in each case comparable to results achieved using conventional room temperature (RT) controls. In further tests with transmons, a qubit-limited error rate of 7.76 × 10−4 per Clifford gate is achieved, again comparable to the results achieved using RT controls. The QSC’s maximum RF output power is −18 dBm, and power dissipation per qubit under active control is 23 mW.
Abstract Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS–based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two–qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single–side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single–qubit gates, and 17.51 IPC for two–qubit gates. A single–qubit error per gate of є1Q=8e-4 and two–qubit error per gate of є2Q=1.4e-2 is shown. A drive–induced Z–rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z–errors is numerically evaluated with a two–qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z–error varies linearly with pulse amplitude.
This chapter will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.
Qubit control electronics composed of CMOS circuits are of critical interest for next-generation quantum computing systems. A CMOS-based application-specific integrated circuit (ASIC) fabricated in 14-nm fin field-effect transistor (FinFET) technology was used to generate and sequence qubit control wave forms and demonstrate a two-qubit cross-resonance gate between fixed-frequency transmons. The controller was thermally anchored to the T=4 K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single-side banded output frequencies between 4.5 and 5.5 GHz, with a maximum power output of −18 dBm. Randomized-benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates and 17.51 IPC for two-qubit gates. A single-qubit error per gate of ϵ1Q=8×10−4 and a two-qubit error per gate of ϵ2Q=1.4×10−2 were shown. A drive-induced Z rotation was observed by way of a rotary-echo experiment; this observation is consistent with the expected qubit behavior given the measured excess local-oscillator (LO) leakage from the CMOS chip. The effect of spurious drive-induced Z errors was numerically evaluated with a two-qubit model Hamiltonian and shown to be in good agreement with the measured RB data. The modeling results suggest that the Z error varies linearly with the pulse amplitude. Published by the American Physical Society 2024
Cryogenic CMOS (Cryo-CMOS) ASICs have drawn increasing attention with great potential in scaling down the quantum computing (QC) platform. Recently, several cryoCMOS ASICs have been presented in the literature, including the qubit state readout ASICs [1–4] and state controller ASICs [5–8]. For readout ASICs, the quadrature down conversion architecture is widely adopted, with the power consumption ranging from 20mW [1] to 75mW [2]. Also, significant progress has been made in reducing the power consumption of qubit controllers. The controller in [5] consumes a power of <4 mW/qubit under active control, when controlling a superconducting quantum computing unit cell. Nevertheless, it remains a long-term goal to reduce the power consumption and promote the integration level of readout/controller ASICs, in consideration of the increasing requirement on qubit number and the limited cooling power provided by the dilution refrigerator.