Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate
Devin Underwood, Joseph A. Glick, Ken Inoue, David J. Frank, John Timmerwilke, Emily Pritchett, Sudipto Chakraborty, Kevin Tien, Mark Yeck, John F. Bulzacchelli, Christian W. Baks, R. P. Robertazzi, Matthew Beck, Rajiv Joshi, Dorothy Wisnieff, Scott Lekuch, B. Gaucher, Daniel J. Friedman, Pat Rosno, Daniel Ramirez, Jeff Ruedinger
Qubit control electronics composed of CMOS circuits are of critical interest for next-generation quantum computing systems. A CMOS-based application-specific integrated circuit (ASIC) fabricated in 14-nm fin field-effect transistor (FinFET) technology was used to generate and sequence qubit control wave forms and demonstrate a two-qubit cross-resonance gate between fixed-frequency transmons. The controller was thermally anchored to the T=4 K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single-side banded output frequencies between 4.5 and 5.5 GHz, with a maximum power output of −18 dBm. Randomized-benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates and 17.51 IPC for two-qubit gates. A single-qubit error per gate of ϵ1Q=8×10−4 and a two-qubit error per gate of ϵ2Q=1.4×10−2 were shown. A drive-induced Z rotation was observed by way of a rotary-echo experiment; this observation is consistent with the expected qubit behavior given the measured excess local-oscillator (LO) leakage from the CMOS chip. The effect of spurious drive-induced Z errors was numerically evaluated with a two-qubit model Hamiltonian and shown to be in good agreement with the measured RB data. The modeling results suggest that the Z error varies linearly with the pulse amplitude. Published by the American Physical Society 2024
Qubit control electronics composed of CMOS circuits are of critical interest for next-generation quantum computing systems. A CMOS-based application-specific integrated circuit (ASIC) fabricated in 14-nm fin field-effect transistor (FinFET) technology was used to generate and sequence qubit control wave forms and demonstrate a two-qubit cross-resonance gate between fixed-frequency transmons. The controller was thermally anchored to the T=4 K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single-side banded output frequencies between 4.5 and 5.5 GHz, with a maximum power output of −18 dBm. Randomized-benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates and 17.51 IPC for two-qubit gates. A single-qubit error per gate of ϵ1Q=8×10−4 and a two-qubit error per gate of ϵ2Q=1.4×10−2 were shown. A drive-induced Z rotation was observed by way of a rotary-echo experiment; this observation is consistent with the expected qubit behavior given the measured excess local-oscillator (LO) leakage from the CMOS chip. The effect of spurious drive-induced Z errors was numerically evaluated with a two-qubit model Hamiltonian and shown to be in good agreement with the measured RB data. The modeling results suggest that the Z error varies linearly with the pulse amplitude. Published by the American Physical Society 2024
Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS-based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two-qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single--side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates, and 17.51 IPC for two-qubit gates. A single-qubit error per gate of ε1Q=8e-4 and two-qubit error per gate of ε2Q=1.4e-2 is shown. A drive-induced Z-rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z-errors is numerically evaluated with a two-qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z-error varies linearly with pulse amplitude.
Abstract Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS–based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two–qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single–side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single–qubit gates, and 17.51 IPC for two–qubit gates. A single–qubit error per gate of є1Q=8e-4 and two–qubit error per gate of є2Q=1.4e-2 is shown. A drive–induced Z–rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z–errors is numerically evaluated with a two–qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z–error varies linearly with pulse amplitude.
A scalable, non-multiplexed cryogenic 14-nm FinFET quantum bit (qubit) state controller (QSC) for use in the semi-autonomous control of superconducting transmon qubits is reported. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low-power current-mode single sideband upconversionI/Qmixer-based RF arbitrary waveform generator (AWG). Implemented in the 14-nm CMOS FinFET technology, the QSC generates control signals in its target 4.5–5.5-GHz-frequency range, achieving an spurious free dynamic range (SFDR) > 50 dB for a signal bandwidth of 500 MHz. With the controller operating in the 4 K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmonT1andT2coherence times were 75.7 and 73μs, respectively, in each case comparable to results achieved using conventional room temperature (RT) controls. In further tests with transmons, a qubit-limited error rate of 7.76 × 10−4 per Clifford gate is achieved, again comparable to the results achieved using RT controls. The QSC’s maximum RF output power is −18 dBm, and power dissipation per qubit under active control is 23 mW.
This chapter will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.
A universal fault-tolerant quantum computer will require large-scale control systems that can realize all the waveforms required to implement a gateset that is universal for quantum computing. Optimization of such a system, which must be precise and extensible, is an open research challenge. Here, we present a cryogenic quantum control integrated circuit (IC) that is able to control all the necessary degrees of freedom of a two-qubit subcircuit of a superconducting quantum processor. Specifically, the IC contains a pair of 4–8-GHz RF pulse generators forXYcontrol, three baseband current generators for qubit and coupler frequency control, and a digital controller that includes a sequencer for gate sequence playback. After motivating the architecture, we describe the circuit-level implementation details and present experimental results. Using standard benchmarking techniques, we show that the cryogenic CMOS (cryo-CMOS) IC is able to execute the components of a gateset that is universal for quantum computing while achieving single-qubitXYandZaverage gate error rates of 0.17%–0.36% and 0.14%–0.17%, respectively, as well as two-qubit average cross-entropy benchmarking (XEB) cycle error rates of 1.2%. These error rates, which were achieved while dissipating just 4 mW/qubit, are comparable to the measured error rates obtained using baseline room-temperature electronics.
Abstract Realizing a practically useful superconducting quantum computer will require a dramatic scale-up of quantum control electronics to meet the growth in required qubit counts. Conventional rack-based room-temperature control electronics impose severe constraints on wiring density, cost, and system footprint, creating a barrier to large-scale and fault-tolerant quantum computing. Here we demonstrate a hybrid quantum control architecture that combines cryogenic complementary metal-oxide semiconductor (cryo‑CMOS) application-specific integrated circuits (ASICs) for two‑qubit flux control with room‑temperature radio‑frequency electronics for single‑qubit control and readout. The resulting system achieves high density and scalable quantum control without compromising two‑qubit gate fidelity. Deployed on a 156‑qubit quantum processor, the cryo-CMOS subsystem achieves two‑qubit gate errors at the {10}^{-3} level, with a best randomized benchmarking error per gate of 8.4\times{10}^{-4}, stable operation over multi‑day timescales, and no measurable performance degradation as we increase the temperature of the cryo-CMOS ASICs from 7 to 20 K. Thermal analysis identifies cryo-CMOS chip operation near 20 K as a favorable regime, enabling efficient cooling of a large number of channels per cryostat. Compared against rack‑based flux-control, the cryo-CMOS subsystem achieves statistically indistinguishable two-qubit gate fidelities under matched gate settings and enables a tenfold improvement in system spatial footprint. These results establish cryo‑CMOS flux control as a practical and scalable foundation for large‑scale and fault-tolerant superconducting quantum systems.